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參數資料
| 型號： | CYK001M16ZCCA |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16-Mbit (1M x 16) Pseudo Static RAM |
| 中文描述： | 16兆位（1米× 16）偽靜態存儲器 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 321K |
| 代理商： | CYK001M16ZCCA |
16-Mbit (1M x 16) Pseudo Static RAM
CYK001M16ZCCA
MoBL3
Cypress Semiconductor Corporation
Document #: 38-05454 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised May 15, 2004
Features
Wide voltage range: 2.70V–3.30V
Access Time: 55 ns, 70 ns
Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 13 mA @ f = f
max
Ultra low standby power
Automatic power-down when deselected
CMOS for optimum speed/power
Deep Sleep Mode
Offered in a 48-ball BGA Package
Functional Description
The CYK001M16ZCCAU is a high-performance CMOS
Pseudo static RAM organized as 1M words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for providing More Battery Life (MoBL
)
in portable applications such as cellular telephones. The
device can be put into standby mode when deselected (CE
HIGH or both BHE and BLE are HIGH). The input/output pins
(I/O
0
through I/O
15
) are placed in a high-impedance state
when: deselected (CE HIGH), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by asserting Chip
Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O
0
through
I/O
7
), is written into the location specified on the address pins
(A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by asserting Chip
Enable (CE)
and Output Enable (OE) inputs LOW while forcing
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O
0
to I/O
7
. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O
8
to
I/O
15
. Refer to the truth table for a complete description of read
and write modes.
This device incorporates a Low Power mode wherein data
integrity is not guaranteed, but Power Consumption reduces
to less than 100
μ
W. This mode (Deep Sleep Mode) is enabled
by driving ZZ LOW.See the Truth Table for a complete
description of Read, Write, and Deep Sleep mode.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
1M × 16
RAM Array
I/O
0
–I/O
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
I/O
8
–I/O
15
WE
BLE
BHE
A
1
A
0
A
9
A
10
PoCircuit
BHE
BLE
CE
CE
A
1
ZZ
A
1
A
1
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相關代理商/技術參數 |
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