- 您現在的位置：買賣IC網 > PDF目錄380222 > CYM1465ALPD-70C (CYPRESS SEMICONDUCTOR CORP) 512K x 8 PDIP Static RAM PDF資料下載
參數資料
| 型號： | CYM1465ALPD-70C |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 8 PDIP Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 70 ns, PDIP32 |
| 封裝： | 0.600 INCH, DIP-32 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 170K |
| 代理商： | CYM1465ALPD-70C |
512K x 8 PDIP Static RAM
CYM1465A
Cypress Semiconductor Corporation
Document #: 38-05269 Rev. **
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised March 15, 2002
65A
Features
4.5V–5.5V operation
CMOS SRAM for optimum speed and power
Low active power (165 mW max.)
Low standby power (L Version)—(110
μ
W max)
2V data retention (L Version)
JEDEC-compatible pinout
32-pin, 0.6-inch-wide DIP package
TTL-compatible inputs and outputs
Functional Description
The CYM1465A is a high-performance CMOS static RAM or-
ganized as 512K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE), an active LOW
Output Enable (OE), and three-state drivers. This device has
an automatic power-down feature that reduces power con-
sumption by more than 99% when deselected.
Writing to the SRAM is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
eight input/output pins (I/O
0
through I/O
7
) of the device is then
written into the memory location specified on the address pins
(A
through A
). Reading from the device is accomplished by
taking chip select (CE) and output enable (OE) LOW while
write enable (WE) remains inactive or HIGH. Under these con-
ditions, the contents of the memory location specified on the
address pins (A
0
through A
18
) will appear on the eight appro-
priate data input/output pins (I/O
0
through I/O
7
).The eight in-
put/output pins (I/O0 through I/O7) are placed in a high imped-
ance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
The CYM1465A is available in a 32-pin 600-mil wide body
PDIP package.
Selection Guide
CYM1465A-70
70
20
20
CYM1465A-85
85
20
20
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (
μ
A)
Logic Block Diagram
Pin Configuration
Top View
DIP
25
24
26
27
28
29
30
31
32
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
S
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
V
CC
A
15
A
17
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
1
A
1
A
A
1
A
4
A
5
A
6
A
7
A
12
A
14
A
16
A
17
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512 x 256 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
2
A
1
A
3
CE
A
8
A
9
A
1
A
1
相關PDF資料 |
PDF描述 |
|---|---|
| CYM1465ALPD-70I | 512K x 8 PDIP Static RAM |
| CYM1465ALPD-85C | 512K x 8 PDIP Static RAM |
| CYM1465ALPD-85I | 512K x 8 PDIP Static RAM |
| CYM1465AL | Memory |
| CYM1465 | 512K x 8 SRAM Module(512K x 8 靜態RAM模塊) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CYM1465ALPD-70I | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:512K x 8 PDIP Static RAM |
| CYM1465ALPD-85C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:512K x 8 PDIP Static RAM |
| CYM1465ALPD-85I | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:512K x 8 PDIP Static RAM |
| CYM1465LPD-100C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM Module |
| CYM1465LPD-120I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM Module |
發布緊急采購，3分鐘左右您將得到回復。