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參數資料
| 型號： | CYM1831PZ-45C |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64K x 32 Static RAM Module |
| 中文描述： | 64K X 32 MULTI DEVICE SRAM MODULE, 45 ns, PZMA64 |
| 封裝： | PLASTIC, ZIP-64 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 246K |
| 代理商： | CYM1831PZ-45C |
64K x 32 Static RAM Module
CYM1831
Cypress Semiconductor Corporation
Document #: 38-05270 Rev. **
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised March 15, 2002
31
Features
High-density 2-Mbit SRAM module
32-bit standard footprint supports densities from 16K
x 32 through 1M x 32
High-speed CMOS SRAMs
—
Access time of 15 ns
Low active power
—
5.3W (max.)
SMD technology
TTL-compatible inputs and outputs
Low profile
—
Max. height of 0.50 in.
Small PCB footprint
—
1.2 sq. in.
Functional Description
The CYM1831 is a high-performance 2-Mbit static RAM mod-
ule organized as 64K words by 32 bits. This module is con-
structed from eight 64K x 4 SRAMs in SOJ packages mounted
on an epoxy laminate board with pins. Four chip selects (CS
1
,
CS
, CS
, and CS
) are used to independently enable the four
bytes. Reading or writing can be executed on individual bytes
or any combination of multiple bytes through proper use of
selects.
Writing to each byte is accomplished when the appropriate
Chip Selects (CS
) and Write Enable (WE) inputs are both
LOW. Data on the input/output pins (I/O
X
) is written into the
memory location specified on the address pins (A
0
through
A
15
).
Reading the device is accomplished by taking the Chip Selects
(CS
) LOW and Output Enable (OE) LOW while Write Enable
(WE) remains HIGH. Under these conditions the contents of
the memory location specified on the address pins will appear
on the data input/output pins (I/O
X
).
The data input/output pins stay in the high-impedance state
when Write Enable (WE) is LOW or the appropriate chip se-
lects are HIGH.
Two pins (PD
and PD
) are used to identify module memory
density in applications where alternate versions of the
JEDEC-standard modules can be interchanged.
Logic Block Diagram
Pin Configuration
A
0
–
A
15
OE
WE
I/O
0
–
I/O
3
CS
3
I/O
4
–
I/O
7
ZIP/SIMM
Top View
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
V
CC
A
6
CS
1
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
WE
A
14
CS
1
CS
2
GND
CS
4
NC
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
16
64K x 4
SRAM
64K x 4
SRAM
4
4
64K x 4
SRAM
64K x 4
SRAM
4
4
64K x 4
SRAM
64K x 4
SRAM
4
4
64K x 4
SRAM
64K x 4
SRAM
4
4
CS
2
CS
4
I/O
8
–
I/O
11
I/O
16
–
I/O
19
I/O
24
–
I/O
27
I/O
12
–
I/O
15
I/O
20
–
I/O
23
I/O
28
–
I/O
31
PD
0
- OPEN
PD
1
- GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
CS
3
NC
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
GND
A
15
I/O
28
I/O
29
I/O
30
I/O
31
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