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參數資料
| 型號： | CYM1836 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 128K x 32 Static RAM Module |
| 中文描述： | 128K的× 32靜態RAM模塊 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 540K |
| 代理商： | CYM1836 |
128K x 32 Static RAM Module
CYM1836
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
February 15, 1999
408-943-2600
Features
High-density 4-megabit SRAM module
32-bit standard footprint supports densities from 16K
x 32 through 1M x 32
High-speed CMOS SRAMs
—Access time of 15 ns
Low active power
—2.6W (max.) at 20 ns
SMD technology
TTL-compatible inputs and outputs
Low profile
—Max. height of 0.57 in.
Small PCB footprint
—0.78 sq. in.
Available in SIMM, ZIP format. SIMM suitable for vertical
or angled sockets.
Functional Description
The CYM1836 is a high-performance 4-megabit static RAM
module organized as 128K words by 32 bits. This module is
constructed from four 128K x 8 SRAMs in SOJ packages
mounted on an epoxy laminate board with pins. Four chip se-
lects (CS
1
, CS
2
, CS
3
, CS
4
) are used to independently enable
the four bytes. Reading or writing can be executed on individ-
ual bytes or any combination of multiple bytes through proper
use of selects.
Writing to each byte is accomplished when the appropriate
Chip Select (CS) and Write Enable (WE) inputs are both
LOW. Data on the input/output pins (I/O) is written into the
memory location specified on the address pins (A
0
through
A
16
).
Reading the device is accomplished by taking the Chip Select
(CS) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location
specified on the address pins will appear on the data in-
put/output pins (I/O).
The data input/output pins stay at the high-impedance state
when write enable is LOW or the appropriate chip selects are
HIGH.
Two pins (PD
0
and PD
1
) are used to identify module mem-
ory density in applications where alternate versions of the
JEDEC-standard modules can be interchanged.
Logic Block Diagram
Pin Configuration
1836–1
A
0
A
16
OE
WE
CS
3
I/O
0
I/O
7
ZIP/SIMM
Top View
CS
1
CS
2
CS
4
I/O
8
I/O
15
I/O
16
I/O
23
I/O
24
I/O
31
17
128K x 8
SRAM
4
SRAM
4
SRAM
4
SRAM
4
PD
0
OPEN
PD
1
OPEN
128K x 8
128K x 8
128K x 8
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
A
14
CS
1
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
CS
2
CS
4
NC
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
CS
3
A
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
GND
1836–2
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