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參數資料
| 型號： | CYM1846V33PZ-35C |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 32 3.3V Static RAM Module |
| 中文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 35 ns, PZMA72 |
| 封裝： | PLASTIC, ZIP-72 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 338K |
| 代理商： | CYM1846V33PZ-35C |
PRELIMINARY
512K x 32 3.3V Static RAM Module
CYM1846V33
Cypress Semiconductor Corporation
Document #: 38-05275 Rev. **
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised March 15, 2002
46V33
Features
High-density 3.3V 16-megabit SRAM module
32-bit Standard Footprint supports densities from
16K x 32 through 2M x 32
High-speed SRAMs
—Access time of 12 ns
Low active power
—1.650W (max.) at 12 ns
72 pins
Available in ZIP, SIMM format
Functional Description
The CYM1846V33 is a high-performance 3.3V 16-megabit
static RAM module organized as 512K words by 32 bits. This
module is constructed from four 512K x 8 SRAMs in SOJ pack-
ages mounted on an epoxy laminate substrate. Four chip se-
lects are used to independently enable the four bytes. Reading
or writing can be executed on individual bytes or any combina-
tion of multiple bytes through proper use of selects.
The CYM1846V33 is designed for use with standard 72-pin
SIMM sockets. The pinout is downward compatible with the
64-pin JEDEC ZIP/SIMM module family (CYM1821,
CYM1831, CYM1836, and CYM1841). Thus, a single mother-
board design can be used to accommodate memory depth
ranging from 16K words (CYM1821) to 1,024K words
(CYM1851). The CYM1846V33 is offered in vertical SIMM
configuration and is available with either tin-lead or 10
micro-inches of gold flash on the edge contacts.
Presence detect pins (PD
0
PD
3
) are used to identify module
memory density in applications where modules with alternate
word depths can be interchanged.
LogicBlockDiagram
Pin Configuration
ZIP/SIMM
Top View
OE
WE
CS
3
CS
1
19
8
8
8
8
CS
2
CS
4
PD
0
- OPEN
PD
1
- OPEN
PD
2
- GND
PD
3
- OPEN
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
NC
PD
3
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
A
4
A
5
PD
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
6
I/O
7
WE
A
14
CS
1
GND
A
15
CS
2
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
CS
3
A
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
NC
I/O
14
I/O
15
CS
4
A
17
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
A
18
NC
NC
A
0
–A
18
I/O
0
–
I/O
7
I/O
7
–
I/O
15
I/O
16
–
I/O
23
I/O
24
–
I/O
31
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