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參數(shù)資料
| 型號： | CYM52KQT36AV25 |
| 英文描述： | Memory |
| 中文描述： | 內存 |
| 文件頁數(shù)： | 1/25頁 |
| 文件大小： | 245K |
| 代理商： | CYM52KQT36AV25 |
ADVANCE INFORMATION
18-Mb Pipelined MCM with QDR
TM
Architecture
CYM52KQT36AV25
Cypress Semiconductor Corporation
Document #: 38-05041 Rev. **
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised August 15, 2001
Features
Separate Independent Read and Write Data Ports
—Supports concurrent transactions
167 MHz Clock for High Bandwidth
—2.5 ns Clock-to-Valid access time
Double Data Rate (DDR) interfaces on both Read &
Write Ports (data transferred at 333 MHz) @167 MHz
Two input clocks (K and K) for precise DDR timing
—SRAM uses rising edges only
Two output clocks (C and C) account for clock skew and
flight time mismatches
Single multiplexed address input bus latches address
inputs for both READ and WRITE ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
2.5V core power supply with HSTL Inputs and Outputs
13x15 mm, 1.0-mm pitch fBGA package, 165 ball (11x15
matrix)
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–1.9V)
JTAG Interface
Variable Impedance HSTL
Functional Description
The CYM52KQT36AV25 is a 2.5V 18M Synchronous Pipe-
lined SRAM equipped with QDR architecture. QDR architec-
ture consists of two separate ports to access the memory ar-
ray. The Read port has dedicated Data Outputs to support
Read operations and the Write Port has dedicated Data inputs
to support Write operations. Access to each port is accom-
plished through a common
address bus. The Read address is
latched on the rising edge of the K clock and the Write address
is latched on the rising edge of K clock. QDR has separate
data inputs and data outputs to completely eliminate the need
to
“
turn-around
”
the data bus required with common I/O devic-
es. Accesses to the CYM52KQT36AV25 Read and Write ports
are completely independent of one another. All accesses are
initiated synchronously on the rising edge of the positive input
clock (K). In order to maximize data throughput, both Read and
Write ports are equipped with Double Data Rate (DDR) inter-
faces. Therefore, data can be transferred into the device on
every rising edge of both input clocks (K and K) AND out of the
device on every rising edge of the output clock (C and C) there-
by maximizing performance while simplifying system design.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Select allows each port to operate inde-
pendently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram
A
(17:0)
K
C
K
D
[35:0]
WPS
BWS
0
BWS
1
18
Vref
18
18
36
D
[17:0]
A
(17:0)
D
[17:0]
A
(17:0)
K
C
BWS
2
BWS
3
K
C
K
C
K
C
C
RPS
Q
[35:0]
Q
[17:0]
RPS
TDI
Q
[17:0]
RPS
Q
[8:0]
Q
[17:9]
Q
[25:18]
Q
[35:26]
D
[8:0]
D
[17:9]
D
[25:18]
D
[35:26]
TDO
TMS
TCLK
TDO
TMS
TCLK
TDI
TCLK
TMS
TDI
TDO
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