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參數資料
| 型號： | CYS25G0101DX-ATXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | SONET OC-48 Transceiver |
| 中文描述： | TRANSCEIVER, PQFP120 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 291K |
| 代理商： | CYS25G0101DX-ATXI |
CYS25G0101DX
SONET OC-48 Transceiver
Cypress Semiconductor Corporation
Document Number: 38-02009 Rev. *K
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised July 27, 2007
Features
I
SONET OC-48 operation
I
Bellcore and ITU jitter compliance
I
2.488 GBaud serial signaling rate
I
Multiple selectable loopback or loop through modes
I
Single 155.52 MHz reference clock
I
Transmit FIFO for flexible data interface clocking
I
16-bit parallel-to-serial conversion in transmit path
I
Serial-to-16-bit parallel conversion in receive path
I
Synchronous parallel interface
LVPECL compliant
HSTL compliant
I
Internal transmit and receive phase-locked loops (PLLs)
I
Differential CML serial input
50 mV input sensitivity
100
Internal termination and DC restoration
I
Differential CML serial output
Source matched for 50
transmission lines (100
differential
transmission lines)
I
Direct interface to standard fiber optic modules
I
Less than 1.0W typical power
I
120-pin 14 mm × 14 mm TQFP
I
Standby power saving mode for inactive loops
I
0.25
μ
BiCMOS technology
I
Pb-free packages available
Functional Description
The CYS25G0101DX SONET OC-48 Transceiver is a commu-
nications building block for high speed SONET data communica-
tions. It provides complete parallel-to-serial and serial-to-parallel
conversion, clock generation, and clock and data recovery
operations in a single chip optimized for full SONET compliance.
Transmit Path
New data is accepted at the 16-bit parallel transmit interface at
a rate of 155.52 MHz. This data is passed to a small integrated
FIFO to allow flexible transfer of data between the SONET
processor and the transmit serializer. As each 16-bit word is read
from the transmit FIFO, it is serialized and sent out to the high
speed differential line driver at a rate of 2.488 Gbits/second.
Receive Path
As serial data is received at the differential line receiver, it is
passed to a clock and data recovery (CDR) PLL that extracts a
precision low jitter clock from the transitions in the data stream.
This bit rate clock is used to sample the data stream and receive
the data. Every 16-bit times, a new word is presented at the
receive parallel interface along with a clock.
Parallel Interface
The parallel I/O interface supports high speed bus communica-
tions using HSTL signaling levels to minimize both power
consumption and board landscape. The HSTL outputs are
capable of driving unterminated transmission lines of less than
70 mm and terminated 50
transmission lines of more than twice
that length.
The CYS25G0101DX Transceiver’s parallel HSTL I/O can also
be configured to operate at LVPECL signaling levels. This is
done externally by changing V
DDQ
, V
REF
and creating a simple
circuit at the termination of the transceiver’s parallel output
interface.
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