
Independent Clock HOTLink II Dual
Serializer and Dual Reclocking Deserializer
CYV15G0204TRB
Cypress Semiconductor Corporation
Document #: 38-02101 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 2, 2007
Features
Second-generation HOTLink
technology
Compliant to SMPTE 292M and SMPTE 259M video
standards
Dual-channel video serializer plus dual channel video
reclocking deserializer
— 195- to 1500-Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
Supports reception of either 1.485 or 1.485/1.001 Gbps data
rate with the same training clock
Supports half-rate and full-rate clocking
Internal phase-locked loops (PLLs) with no external PLL
components
Selectable differential PECL-compatible serial inputs
— Internal DC-restoration
Redundant differential PECL-compatible serial outputs
— No external bias resistors required
— Signaling-rate controlled edge-rates
— Internal source termination
Synchronous LVTTL parallel interface
JTAG boundary scan
Built-In Self-Test (BIST) for at-speed link testing
Link Quality Indicator
— Analog signal detect
— Digital signal detect
Low-power 2.5W @ 3.3V typical
Single 3.3V supply
Thermally enhanced BGA
Pb-Free package option available
0.25
μ
BiCMOS technology
Functional Description
The CYV15G0204TRB Independent Clock HOTLink II Dual
Serializer and Dual Reclocking Deserializer is a point-to-point
or point-to-multipoint communications building block enabling
transfer of data over a variety of high-speed serial links
including SMPTE 292M and SMPTE 259M video applications.
It supports signaling rates in the range of 195 to 1500 Mbps
per serial link. All transmit and receive channels are
independent and can operate simultaneously at different
rates. Each transmit channel accepts 10-bit parallel characters
in an Input Register and converts them to serial data. Each
receive channel accepts serial data and converts it to 10-bit
parallel characters and presents these characters to an Output
Register. The received serial data can also be reclocked and
retransmitted through the reclocker serial outputs.
Figure 1
illustrates typical connections between independent video
co-processors and corresponding CYV15G0204TRB chips.
The CYV15G0204TRB satisfies the SMPTE 259M and
SMPTE 292M compliance as per SMPTE EG34-1999 Patho-
logical Test Requirements.
As
a
second-generation
CYV15G0204TRB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data and BIST) with other HOTLink
devices. Each transmit (TX) channel of the CYV15G0204TRB
HOTLink II device accepts scrambled 10-bit transmission
characters. These characters are serialized and output from
dual Positive ECL (PECL) compatible differential trans-
mission-line drivers at a bit-rate of either 10- or 20-times the
input reference clock for that channel.
HOTLink
device,
the
Figure 1. HOTLink II System Connections
Independent
Channel
CYV15G0204TRB
V
10
10
10
V
10
10
10
10
Serial Links
CYVChannel
Device
Independent
Device
Reclocked
Outputs
Reclocked
Outputs
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