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參數(shù)資料
型號(hào): CYW15G0403DXB
廠商: Cypress Semiconductor Corp.
英文描述: Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘,四熱連接II收發(fā)器)
中文描述: 獨(dú)立時(shí)鐘四路HOTLink II收發(fā)器(獨(dú)立時(shí)鐘,四熱連接二收發(fā)器)
文件頁(yè)數(shù): 1/43頁(yè)
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代理商: CYW15G0403DXB
Independent Clock Quad HOTLink II Transceiver
CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Cypress Semiconductor Corporation
Document #: 38-02065 Rev. *E
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised July 8, 2005
Features
Second-generation HOTLink
technology
Compliant to multiple standards
—ESCON, DVB-ASI, SMPTE-292M, SMPTE-259M,
Fibre Channel and Gigabit Ethernet (IEEE802.3z)
—CPRI compliant
—CYW15G0403DXB compliant to OBSAI-RP3
—8B/10B coded data or 10 bit uncoded data
Quad channel transceiver operates from 195 to
1500 MBaud serial data rate
—CYW15G0403DXB operates from 195 to 1540 MBaud
—Aggregate throughput of up to 12 Gbits/second
Second-generation HOTLink
technology
Truly independent channels
—Each channel can operate at a different signaling
rate
—Each channel can transport a different type of data
Selectable input/output clocking options
Internal phase-locked loops (PLLs) with no external
PLL components
Dual differential PECL-compatible serial inputs per
channel
—Internal DC-restoration
Dual differential PECL-compatible serial outputs per
channel
—Source matched for 50
transmission lines
—No external bias resistors required
—Signaling-rate controlled edge-rates
MultiFrame Receive Framer provides alignment
options
—Bit and byte alignment
—Comma or Full K28.5 detect
—Single or Multi-byte Framer for byte alignment
—Low-latency option
Synchronous LVTTL parallel interface
JTAG boundary scan
Built-In Self-Test (BIST) for at-speed link testing
Compatible with
—Fiber-optic modules
—Copper cables
—Circuit board traces
Per-channel Link Quality Indicator
—Analog signal detect
—Digital signal detect
Low-power 3W @ 3.3V typical
Single 3.3V supply
256-ball thermally enhanced BGA
Pb-Free package option available
0.25
μ
BiCMOS technology
Functional Description
The CYP(V)15G0403DXB
[1]
Independent Clock Quad
HOTLink II Transceiver is a point-to-point or point-to-multi-
point communications building block enabling transfer of data
over a variety of high-speed serial links like optical fiber,
balanced, and unbalanced copper transmission lines. The
signaling rate can be anywhere in the range of 195 to 1500
MBaud per serial link. Each channel operates independently
with its own reference clock allowing different rates. Each
transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and then
converts it to serial data. Each receive channel accepts serial
data and converts it to parallel data, decodes the data into
characters, and presents these characters to an Output
Register.
Figure 1
illustrates typical connections between
independent
host
systems
CYP(V)(W)15G0403DXB chips.
and
corresponding
Note:
1.
CYV15G0403DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0403DXB refers to OBSAI RP3 compliant devices (maximum
operating data rate is 1540 MBaud). CYP15G0403DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and
also OBSAI RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0403DXB refers to all three devices.
Figure 1. HOTLink II System Connections
S
Serial Links
10
10
10
10
10
10
10
10
S
10
10
10
10
10
10
10
10
Serial Links
Serial Links
Serial Links
Backplane or
Cabled
Connections
Independent
CYP(V)(W)15G0403DXB
CYP(V)(W)15G0403DXB
Independent
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