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參數資料
| 型號： | CYW3335 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 諧振器 |
| 英文描述： | Dual Serial Input PLL with 2.5-GHz Prescalers(帶2.5-GHz 預標定器的串聯輸入PLL) |
| 中文描述： | DUAL PRESCALER, PDSO20 |
| 封裝： | 0.173 INCH, MO-153, TSSOP-20 |
| 文件頁數： | 1/10頁 |
| 文件大?。?/td> | 158K |
| 代理商： | CYW3335 |
Dual Serial Input PLL with 2.5-GHz Prescalers
CYW3335
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
February 14, 2000, rev. **
Features
Operating voltage 2.7V to 5.5V
PLL1 and PLL2 operating frequency:
—2.5 GHz with prescaler ratios of 32/33 or 64/65
Lock detect feature
Power-down mode I
CC
< 1 μA typical at 3.0V
20-pin TSSOP (Thin Shrink Small Outline Package)
Applications
The Cypress CYW3335 is a dual serial input PLL frequency
synthesizer designed to combine the Transmit and Receive RF
frequency sections of wireless communications systems. Two
2.5-GHz prescalers, each with pulse swallow capability are in-
cluded. The device operates from 2.7V and dissipates only
38 mW.
CYW3335 Dual Hi-Lo PLL Block Diagram
Pin Configuration
Binary 7-Bit
Swallow Counter
Prescaler
32/33 or
64/65
Phase
Detector
19-Bit
Latch
Pwr-dwn
PLL1
Binary 11-Bit
Programmable Counter
20-Bit Latch
20-Bit Latch
Prescaler
32/33 or
64/65
Cntrl 22-Bit
Shift
Reg.
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
19-Bit
Latch
Pwr-dwn
PLL2
15-Bit
Reference Counter
15-Bit
Reference Counter
Phase
Detector
Charge
Pump
fr fp
Monitor
Output
Selector
Charge
Pump
Power
Control
GND (17)
V
P
2 (19)
GND (9)
GND (14)
GND (4)
GND (7)
V
CC
1 (1)
V
CC
2 (20)
F
IN
1 (5)
F
IN
1# (6)
OSC_IN (8)
LE (13)
DATA (12)
CLOCK (11)
F
IN
2 (16)
F
IN
2# (15)
V
P
1 (2)
D
O
PLL1 (3)
F
O
/LD (10)
D
O
PLL2 (18)
Latch
Selector
fp1
fr1
fr2
fp2
V
CC
2
V
P
2
D
O
PLL2
GND
F
IN
2
F
IN
2#
GND
LE
DATA
CLOCK
20
19
18
17
16
15
14
13
12
11
V
CC
1
V
P
1
D
O
PLL1
GND
F
IN
1
F
IN
1#
GND
OSC_IN
GND
F
O
/LD
1
2
3
4
5
6
7
8
9
10
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