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參數資料
| 型號： | D80530C |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數： | 1/4頁 |
| 文件大?。?/td> | 74K |
| 代理商： | D80530C |
March 21, 2000
3-1
CAST, Inc.
24 White Birch Drive
Pomona, New York 10907 USA
Phone:
+1 914-354-4945
Fax:
+1 914-354-0325
E-Mail:
info@cast-inc.com
URL:
www.cast-inc.com
Features
8-Bit Control Unit
8-Bit Arithmetic Logic Unit
32-bit Input/Output ports
Two 16-bit Timer/Counters
Interrupt Controller
Internal Data Memory interface can address up to 256
bytes of Read/Write Data Memory Space
External Memory interface can address up to 64K bytes
of External Program Memory Space and up to 64K
bytes of External Data Memory Space
Dual Data Pointer
Variable length MOVX instruction to access fast/slow
RAM or peripherals
Special Function Registers (SFR) interface
Early-warning power-fail interrupt
Applications
Embedded microcontroller systems
Data computation and transfer
Communication systems
Professional audio and video
AllianceCORE Facts
Core Specifics
See Table 1
Provided with Core
Core Specification, Instruction Set
Details, Test Set Details
Design File Formats
.ngo, EDIF Netlist, VHDL Source
Documentation
RTL available at extra cost
Constraints File
Verification
Instantiation
Templates
Reference Designs &
Application Notes
Additional Items
D80530C.ucf
VHDL testbench
VHDL, Verilog
Example design,
assembler programs
Synthesis and simulation scripts
Simulation Tool Used
1076-Compliant VHDL Simulator,
Verilog Simulator
Support
Support provided by CAST, Inc.
Table 1: Core Implementation Data
Supported
Family
Spartan-II
Virtex-E
Virtex
Notes:
1. Optimized for speed
2. Assuming all core I/Os are routed off-chip
Device
Tested
2S150-6
V200E-8
V200-6
CLB
Slices
1
1515
1515
1515
Clock
IOBs
2
1
1
1
IOBs
2
Performance
(MHz)
51
66
52
Xilinx
Tools
M2.1i
M2.1i
M2.1i
Special
Features
None
None
None
143
143
143
Compact D80530C
Microcontroller
March 21, 2000
Product Specification
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