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參數(shù)資料
| 型號： | DAC1330X |
| 英文描述： | DAC1330X 3.3V 12BIT 2MSPS DAC|Data Sheet |
| 中文描述： | DAC1330X 3.3V的12位2MSPS援會|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大小： | 228K |
| 代理商： | DAC1330X |
GENERAL
DESCRIPTION
FEATURES
TYPICAL
APPLICATION
FUNCTIONAL BLOCK DIAGRAM
This core is a CMOS quad-channel 10bit
75MSPS D/A converter for general & video
applications.
The
dac1350x
core
is
implemented in the Samsung 0.18um 3.3V
CMOS process.
Digital inputs are coded as
straight binary. Each dac channel includes
dependent
power
down
control
and
the
ability
to
sense
output
load.
An
external(optional) or internal 0.7V reference
voltage (VREFOUT) and a single external
resister define the full-scale output current
together. It uses the two architecture of
current-segment and binary-weighted.
Maximum conversion rate is 75MSPS
+3.3V CMOS monolithic construction
±1 LSB differential linearity (max)
±2 LSB integral
linearity (max)
External or internal voltage reference
(Including Band Gap Reference Block)
10-Bit parallel digital input
DAC auto-load detection circuitry
Temperature : 0 ~ 70°C
Each channel Power_Down
Power Dump Mode
High Definition Television(HDTV)
High Resolution Color Graphics
Image Processing
Ver 1.5 (Apr. 2002)
No responsibility is assumed by SEC for its use nor for any infringements of
patents or other rights of third parties that may result from its use. The
content of this data sheet is subject to change without any notice.
10BIT 75MSPS Quad-DAC
DAC1350X
SAMSUNG ELECTRONICS Co. LTD
1 / 15
DLDSEL[1:0]
AVDD33A
AVSS33A
AVDD33D
AVSS33D
AVDD18D
Band gap reference
generator
Auto-load
Detect
digital
decode
binary
LSBs
segmented
MSBs
digital
decode
binary
LSBs
segmented
MSBs
digital
decode
binary
LSBs
segmented
MSBs
digital
decode
binary
LSBs
segmented
MSBs
CCOMP
VREFOUT
VBIAS
CLK
DTOUT
DACPRE
DATA0[9:0]
PDDAC[0]
DATA1[9:0]
PDDAC[1]
DATA2[9:0]
PDDAC[2]
DATA3[9:0]
PDDAC[3]
IOUT0 IOUT1 IOUT2 IOUT3
BGPD
DACLP[0]
DACLP[1]
DACLP[2]
DACLP[3]
IRSET
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