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參數(shù)資料
型號(hào): DAC8043FSZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 1/16頁(yè)
文件大?。?/td> 0K
描述: IC DAC 12BIT MULT SRL INP 8SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 47
設(shè)置時(shí)間: 250ns
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 500µW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極
采樣率(每秒): 366k
12-Bit Serial Input Multiplying CMOS
Digital-to-Analog Converter
DAC8043
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2011 Analog Devices, Inc. All rights reserved.
FEATURES
12-bit accuracy in an 8-lead PDIP and SOIC package
Fast serial data input
Double data buffers
Low ± LSB maximum INL and ±1 LSB maximum DNL
Maximum gain error: 2 LSB
Low ±5 ppm/°C maximum tempco
ESD resistant
Low cost
Available in die form
APPLICATIONS
Autocalibration systems
Process control and industrial automation
Programmable amplifiers and attenuators
Digitally controlled filters
FUNCTIONAL BLOCK DIAGRAM
12-BIT DAC
12-BIT
DAC REGISTER
12-BIT
SHIFT REGISTER
12
DAC8043
RFB
VREF
LD
CLK
SRI
GND
VDD
IOUT
RFB
00271-
001
Figure 1.
GENERAL DESCRIPTION
The DAC8043 is a high accuracy 12-bit CMOS multiplying
DAC in a space-saving 8-lead PDIP package. Featuring serial
data input, double buffering, and excellent analog performance,
the DAC8043 is ideal for applications where PC board space is
at a premium. In addition, improved linearity and gain error
performance permit reduced parts count through the elimination
of trimming components. Separate input clock and load DAC
control lines allow full user control of data loading and analog
output.
The circuit consists of a 12-bit serial-in, parallel-out shift register,
a 12-bit DAC register, a 12-bit CMOS DAC, and control logic.
Serial data is clocked into the input register on the rising edge
of the CLK pulse. When the new data word has been clocked
in, it is loaded into the DAC register with the LD input pin.
Data in the DAC register is converted to an output current by
the digital-to-analog converter (DAC).
The fast interface timing of the DAC8043 may reduce timing
design considerations while minimizing microprocessor wait
states. For applications requiring an asynchronous clear function
or more versatile microprocessor interface logic, refer to the
Operating from a single 5 V power supply, the DAC8043 is the
ideal low power, small size, high performance solution to many
application problems. It is available in a PDIP package that is
compatible with auto-insertion equipment. There is also a
16-lead SOIC package available.
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