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參數資料
型號: DC1370A-D
廠商: Linear Technology
文件頁數: 1/34頁
文件大小: 0K
描述: BOARD DEMO 65MSPS LTC2258-14
軟件下載: QuikEval II System
設計資源: DC1370A Design Files
標準包裝: 1
系列: *
相關產品: DC718C-ND - DEMO QUIKEVAL-II DATA
1
225814fc
LTC2258-14
LTC2257-14/LTC2256-14
For more information www.linear.com/LTC2258-14
Typical applicaTion
FeaTures
applicaTions
DescripTion
14-Bit, 65/40/25Msps
Ultralow Power 1.8V ADCs
n
Communications
n
Cellular Base Stations
n
Software Defined Radios
n
Portable Medical Imaging
n
Multi-Channel Data Acquisition
n
Nondestructive Testing
L
, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
74dB SNR
n
88dB SFDR
n
Low Power: 81mW/49mW/35mW
n
Single 1.8V Supply
n
CMOS, DDR CMOS or DDR LVDS Outputs
n
Selectable Input Ranges: 1VP-P to 2VP-P
n
800MHz Full-Power Bandwidth S/H
n
Optional Data Output Randomizer
n
Optional Clock Duty Cycle Stabilizer
n
Shutdown and Nap Modes
n
Serial SPI Port for Configuration
n
Pin Compatible 14-Bit and 12-Bit Versions
n
40-Pin (6mm × 6mm) QFN Package
pling 14-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. They are perfect
for demanding communications applications with AC
performance that includes 74dB SNR and 88dB spurious
free dynamic range (SFDR). Ultralow jitter of 0.17psRMS
allows undersampling of IF frequencies with excellent
noise performance.
DC specs include ±1LSB INL (typical), ±0.3LSB DNL (typi-
cal)andnomissingcodesovertemperature.Thetransition
noise is a low 1.13LSBRMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC+ and ENCinputs may be driven differentially
or single ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
LTC2258-14 2-Tone FFT,
fIN = 68MHz and 69MHz
+
INPUT
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
D13
D0
65MHz
CLOCK
ANALOG
INPUT
225814 TA01a
CMOS
OR
LVDS
1.2V
TO 1.8V
1.8V
VDD
OVDD
OGND
GND
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE
(dBFS) –50
–30
–40
–20
–10
0
10
20
30
225814 TA01b
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參數描述
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