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參數資料
| 型號： | DC1370A-F |
| 廠商： | Linear Technology |
| 文件頁數： | 8/34頁 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 25MSPS LTC2256-14 |
| 軟件下載： | QuikEval II System |
| 設計資源： | DC1370A Design Files |
| 標準包裝： | 1 |
| 系列： | * |
| 相關產品： | DC718C-ND - DEMO QUIKEVAL-II DATA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
LTC2258-14
LTC2257-14/LTC2256-14
16
225814fc
For more information www.linear.com/LTC2258-14
pin FuncTions
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0 to D13 (Pins 17-24, 29-34): Digital Outputs. D13 is
the MSB.
CLKOUT– (Pin 27): Inverted version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the digital outputs by programming the mode
control registers.
DNC (Pin 35): Do not connect this pin.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0_1 to D12_13 (Pins 18, 20, 22, 24, 30, 32, 34): Double
Data Rate Digital Outputs. Two data bits are multiplexed onto
eachoutputpin.Theevendatabits(D0,D2,D4,D6,D8,D10,
D12) appear when CLKOUT+ is low. The odd data bits (D1,
D3, D5, D7, D9, D11, D13) appear when CLKOUT+ is high.
CLKOUT– (Pin 27): Inverted version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling and ris-
ing edges of CLKOUT+. The phase of CLKOUT+ can also
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 19, 21, 23, 29, 31, 33, 35): Do not con-
nect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100 Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1–/D0_1+ to D12_13–/D12_13+ (Pins 17/18, 19/20,
21/22, 23/24, 29/30, 31/32, 33/34): Double Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (D0, D2, D4,
D6, D8, D10, D12) appear when CLKOUT+ is low. The odd
data bits (D1, D3, D5, D7, D9, D11, D13) appear when
CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 27/28): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
OF–/OF+ (Pins 35/36): Over/Under Flow Digital Output.
OF+ is high when an overflow or underflow has occurred.
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相關代理商/技術參數 |
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| DC1370A-G | 制造商:Linear Technology 功能描述:12BIT ADC Eval Brd, Rq. DC1371 & DC1075 制造商:Linear Technology 功能描述:12BIT ADC Eval Brd, Rq. DC1371 & DC1075; Silicon Manufacturer:Linear Technology; Silicon Core Number:LTC2261-12; Kit Application Type:Data Converter; Application Sub Type:ADC; Kit Contents:Board, Guide |
| DC1370A-H | 制造商:Linear Technology 功能描述:12BIT ADC Eval Brd, Rq. DC1371 & DC1075 制造商:Linear Technology 功能描述:12BIT ADC Eval Brd, Rq. DC1371 & DC1075; Silicon Manufacturer:Linear Technology; Silicon Core Number:LTC2260-12; Kit Application Type:Data Converter; Application Sub Type:ADC; Kit Contents:Board, Guide |
| DC1370A-I | 制造商:Linear Technology 功能描述:12BIT ADC Eval Brd, Rq. DC1371 & DC1075 制造商:Linear Technology 功能描述:12BIT ADC Eval Brd, Rq. DC1371 & DC1075; Silicon Manufacturer:Linear Technology; Silicon Core Number:LTC2259-12; Kit Application Type:Data Converter; Application Sub Type:ADC; Kit Contents:Board, Guide |
| DC1370A-J | 功能描述:BOARD DEMO 65MSPS LTC2258-12 RoHS:是 類別:未定義的類別 >> 其它 系列:* 標準包裝:1 系列:* 其它名稱:MS305720A |
| DC1370A-K | 功能描述:BOARD DEMO 40MSPS LTC2257-12 RoHS:是 類別:未定義的類別 >> 其它 系列:* 標準包裝:1 系列:* 其它名稱:MS305720A |
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