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參數資料
| 型號： | DC1525A-B |
| 廠商： | Linear Technology |
| 文件頁數： | 17/34頁 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 105MSPS LTC2174-14 |
| 軟件下載： | QuikEval II System |
| 設計資源： | DC1525A Design Files |
| 標準包裝： | 1 |
| 系列： | * |
| 相關產品： | DC1371A-ND - BOARD USB DATA ACQUISITION HS |
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LTC2175-14/
LTC2174-14/LTC2173-14
24
21754314fa
Table 2. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
>1.000000V
+0.999878V
+0.999756V
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1110
+0.000122V
+0.000000V
–0.000122V
–0.000244V
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
–0.999878V
–1.000000V
<–1.000000V
00 0000 0000 0001
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
applicaTions inForMaTion
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
and all other bits. The FR and DCO outputs are not affected.
Theoutputrandomizerisenabledbyseriallyprogramming
mode control register A1.
Digital Output Test Pattern
To allow in-circuit testing of the digital interface to the
A/D, there is a test mode that forces the A/D data outputs
(D13-D0) of all channels to known values. The digital
output test patterns are enabled by serially programming
mode control registers A3 and A4. When enabled, the test
patterns override all other formatting modes: 2’s comple-
ment and randomizer.
Output Disable
Thedigitaloutputsmaybedisabledbyseriallyprogramming
mode control register A2. The current drive for all digital
outputs including DCO and FR are disabled to save power
or enable in-circuit testing. When disabled the common
mode of each output pair becomes high impedance, but
the differential impedance may remain low.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire chip is powered down, re-
sultingin1mWpowerconsumption.Sleepmodeisenabled
by mode control register A1 (serial programming mode),
or by SDI (parallel programming mode). The amount of
time required to recover from sleep mode depends on the
size of the bypass capacitors on VREF, REFH, and REFL.
For the suggested values in Figure 8, the A/D will stabilize
after 2ms.
In nap mode any combination of A/D channels can be
powered down while the internal reference circuits and the
PLL stay active, allowing faster wakeup than from sleep
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclusive-
OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied
—an exclusive-OR operation is applied between the LSB
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