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參數資料
| 型號： | DC1525A-F |
| 廠商： | Linear Technology |
| 文件頁數： | 16/34頁 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 25MSPS LTC2170-14 |
| 軟件下載： | QuikEval II System |
| 設計資源： | DC1525A Design Files |
| 標準包裝： | 1 |
| 系列： | * |
| 相關產品： | DC1371A-ND - BOARD USB DATA ACQUISITION HS |
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LTC2172-14/
LTC2171-14/LTC2170-14
23
21721014fb
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12 and 13).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be taken
above VDD (up to 3.6V), and the common mode range
is from 1.1V to 1.6V. In the differential encode mode,
ENC– should stay at least 200mV above ground to avoid
falsely triggering the single-ended encode mode. For
good jitter performance ENC+ should have fast rise and
fall times.
The single-ended encode mode should be used with
CMOS encode inputs. To select this mode, ENC– is con-
nected to ground and ENC+ is driven with a square wave
encode input. ENC+ can be taken above VDD (up to 3.6V)
so 1.8V to 3.3V CMOS logic levels can be used. The
ENC+ threshold is 0.9V. For good jitter performance
ENC+ should have fast rise and fall times.
Clock PLL and Duty Cycle Stabilizer
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25s to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
applicaTions inForMaTion
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
DIGITAL OUTPUTS
The digital outputs of the LTC2172-14/LTC2171-14/
LTC2170-14 are serialized LVDS signals. Each chan-
nel outputs two bits at a time (2-lane mode) or one
bit at a time (1-lane mode). The data can be serialized
with 16-, 14-, or 12-bit serialization (see the Timing
Diagrams section for details). Note that with 12-bit
serialization the two LSBs are not available—this mode
is included for compatibility with the 12-bit versions
of these parts.
The output data should be latched on the rising and
falling edges of the data clockout (DCO). A data frame
output (FR) can be used to determine when the data
from a new conversion result begins. In the 2-lane, 14-
bit serialization mode, the frequency of the FR output
is halved.
The maximum serial data rate for the data outputs is
1Gbps, so the maximum sample rate of the ADC will de-
pend on the serialization mode as well as the speed grade
of the ADC (see Table 1). The minimum sample rate for
all serialization modes is 5Msps.
Figure 12. Sinusoidal Encode Drive
Figure 13. PECL or LVDS Encode Drive
50
100
0.1F
T1
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50
LTC2172-14
217214 F12
ENC–
ENC+
ENC+
ENC–
PECL OR
LVDS
CLOCK
0.1F
217214 F13
LTC2172-14
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