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參數資料
| 型號： | DC1620A-L |
| 廠商： | Linear Technology |
| 文件頁數： | 7/38頁 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 25MSPS LTC2140-14 |
| 軟件下載： | QuikEval II System |
| 設計資源： | DC1620A Design Files DC1620A Schematic |
| 標準包裝： | 1 |
| 系列： | * |
| 相關產品： | DC890B-ND - BOARD USB DATA COLLECTION |
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15
21421014fa
LTC2142-14/
LTC2141-14/LTC2140-14
PIN FUNCTIONS
SENSE (Pin 63): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 VSENSE.
Ground (Exposed Pad Pin 65): The exposed pad must be
soldered to the PCB ground.
FULL RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels
(OGND to OVDD)
D2_0 to D2_13 (Pins 25, 26, 27, 28, 29, 30, 31, 32, 33,
34, 35, 36, 37, 38): Channel 2 Digital Outputs. D2_13 is
the MSB.
DNC (Pins 23, 24, 43, 44): Do not connect these pins.
CLKOUT– (Pin 39): Inverted Version of CLKOUT+.
CLKOUT+ (Pin 40): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the digital outputs by programming the mode
control registers.
D1_0 to D1_13 (Pins 45, 46, 47, 48, 49, 50, 51, 52, 53,
54, 55, 56, 57, 58): Channel 1 Digital Outputs. D1_13 Is
the MSB.
OF2 (Pin 59): Channel 2 Over/Underflow Digital Output. OF2
is high when an overflow or underflow has occurred.
OF1 (Pin 60): Channel 1 Over/Underflow Digital Output. OF1
is high when an overflow or underflow has occurred.
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels
(OGND to OVDD)
D2_0_1 to D2_12_13 (Pins 26, 28, 30, 32, 34, 36, 38):
Channel 2 Double Data Rate Digital Outputs. Two data bits
are multiplexed onto each output pin. The even data bits
(D0, D2, D4, D6, D8, D10, D12) appear when CLKOUT+
is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13)
appear when CLKOUT+ is high.
DNC (Pins 23, 24, 25, 27, 29, 31, 33, 35, 37, 43, 44, 45,
47, 49, 51, 53, 55, 57, 59): Do not connect these pins.
CLKOUT– (Pin 39):
Inverted Version of CLKOUT+.
CLKOUT+ (Pin 40): Data Output Clock. The digital outputs
normally transition at the same time as the falling and ris-
ing edges of CLKOUT+. The phase of CLKOUT+ can also
be delayed relative to the digital outputs by programming
the mode control registers.
D1_0_1 to D1_12_13 (Pins 46, 48, 50, 52, 54, 56, 58):
Channel 1 Double Data Rate Digital Outputs. Two data bits
are multiplexed onto each output pin. The even data bits
(D0, D2, D4, D6, D8, D10, D12) appear when CLKOUT+
is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13)
appear when CLKOUT+ is high.
OF2_1 (Pin 60): Over/Underflow Digital Output. OF2_1 is
high when an overflow or underflow has occurred. The
over/underflow for both channels are multiplexed onto
this pin. Channel 2 appears when CLKOUT+ is low, and
Channel 1 appears when CLKOUT+ is high.
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level Is Programmable. There Is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D2_0_1–/D2_0_1+ to D2_12_13–/D2_12_13+ (Pins
25/26, 27/28, 29/30, 31/32, 33/34, 35/36, 37/38): Chan-
nel 2 Double Data Rate Digital Outputs. Two data bits are
multiplexed onto each differential output pair. The even
data bits (D0, D2, D4, D6, D8, D10, D12) appear when
CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9,
D11, D13) appear when CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 39/40): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
DNC (Pins 23, 24, 43, 44): Do not connect these pins.
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| DC1620A-M | 功能描述:BOARD DEMO 125MSPS LTC2145-12 RoHS:是 類別:未定義的類別 >> 其它 系列:* 標準包裝:1 系列:* 其它名稱:MS305720A |
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