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參數(shù)資料
| 型號(hào)： | DDU12H-50C4 |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 延遲線 |
| 英文描述： | 5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| 中文描述： | ACTIVE DELAY LINE, TRUE OUTPUT, PDSO24 |
| 封裝： | SMD-24 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大小： | 235K |
| 代理商： | DDU12H-50C4 |
DDU12H
5-TAP, ECL-INTERFACED
FIXED DELAY LINE
(SERIES DDU12H)
FEATURES
PACKAGES
Ten equally spaced outputs
Fits in 300 mil 32-pin DIP socket
Input & outputs fully 10KH-ECL interfaced & buffered
FUNCTIONAL DESCRIPTION
data
delay
devices, inc.
3
32
31
30
29
24
23
22
21
1
3
4
5
8
9
11
12
16
GND
T2
T4
IN
VEE
GND
T2
T4
VEE
GND
T1
T3
T5
GND
T6
T8
T10
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
T2
T4
IN
N/C
VEE
GND
N/C
T7
T8
VEE
GND
T1
T3
T5
N/C
GND
N/C
T6
T8
T10
DDU12H-xx
DIP
DDU12H-xxM Military DIP
DDU12H-xxC4
SMD
DDU12H-xxMC4 Mil SMD
The DDU12H-series device is a 10-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T10), shifted in time by
an amount determined by the device dash number (See Table). For dash
numbers less than 20, the total delay of the line is measured from T1 to
T10. The nominal tap-to-tap delay increment is given by one-ninth of the
total delay, and the inherent delay from IN to T1 is nominally 1.5ns. For dash numbers greater than or
equal to 20, the total delay of the line is measured from IN to T10. The nominal tap-to-tap delay increment
is given by one-tenth of this number.
PIN DESCRIPTIONS
IN
Signal Input
T1-T10 Tap Outputs
VEE
-5 Volts
GND
Ground
SERIES SPECIFICATIONS
DASH NUMBER SPECIFICATIONS
Part
Number
Total
Delay (ns)
Delay Per
Tap (ns)
DDU12H-10
9
± 1.0 *
1.0
± 0.3
DDU12H-20
20
± 2.0
2.0
± 0.4
DDU12H-25
25
± 2.0
2.5
± 0.4
DDU12H-40
40
± 2.0
4.0
± 0.5
DDU12H-50
50
± 2.5
5.0
± 1.0
DDU12H-75
75
± 4.0
7.5
± 1.5
DDU12H-100
100
± 5.0
10.0
± 2.0
DDU12H-150
150
± 7.5
15.0
± 2.0
DDU12H-200
200
± 10.0
20.0
± 2.0
DDU12H-250
250
± 12.5
25.0
± 2.0
DDU12H-300
300
± 15.0
30.0
± 2.0
DDU12H-400
400
± 20.0
40.0
± 2.0
DDU12H-500
500
± 25.0
50.0
± 2.5
DDU12H-750
750
± 37.5
75.0
± 4.0
DDU12H-1000
1000
± 50.0
100.0
± 5.0
DDU12H-1500
1500
± 75.0
150.0
± 7.0
* Total delay is referenced to first tap output
Input to first tap = 1.5ns
± 1ns
NOTE: Any dash number between 10 and 1500
not shown is also available.
Minimum input pulse width: 10% of total delay
Output rise time: 2ns typical
Supply voltage:
-5VDC
± 5%
Power dissipation: 400mw typical (no load)
Operating temperature: -30
° to 85° C
Temp. coefficient of total delay: 100 PPM/
°C
10%
VCC
GND
IN
T1
T2
T3
T4
T10
Functional diagram for dash numbers < 20
1.5ns
10%
T5
T6
T7
T8
10%
T9
10%
VCC
GND
IN
T1
T2
T3
T4
T10
Functional diagram for dash numbers >= 20
10%
T5
T6
T7
T8
10%
T9
10%
1997 Data Delay Devices
Doc #97036
DATA DELAY DEVICES, INC.
1
5/3/2006
3 Mt. Prospect Ave. Clifton, NJ 07013
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DDU12H-50MC4 | 5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-750 | 5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-750C4 | 5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-750MC4 | 5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-75C4 | 5-TAP, ECL-INTERFACED FIXED DELAY LINE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDU12H-50M | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-50MC3 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) |
| DDU12H-50MC4 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-75 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H750 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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