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參數資料
| 型號： | DDU7F-50A2 |
| 英文描述： | Delay Line |
| 中文描述： | 延遲線 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 74K |
| 代理商： | DDU7F-50A2 |
DDU7F
Doc #97016
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
10-TAP, TTL-INTERFACED
FIXED DELAY LINE
(SERIES DDU7F)
FEATURES
PACKAGES
Ten equally spaced outputs
Fits standard 14-pin DIP socket
Low profile
Auto-insertable
Input & outputs fully TTL interfaced & buffered
10 T
2
L fan-out capability
FUNCTIONAL DESCRIPTION
The DDU7F-series device is a 10-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T10), shifted in time by an
amount determined by the device dash number. The nominal tap-to-tap
delay increment is given by 1/10 of the dash number. For dash numbers
less than 50, the total delay of the line is measured from T1 to T10, with the
nominal value given by 9 times the increment. The inherent delay from IN to T1 is nominally 3.5ns. For
dash numbers greater than or equal to 50, the total delay of the line is measured from IN to T10, with the
nominal value given by the dash number.
SERIES SPECIFICATIONS
Minimum input pulse width:
20% of total delay
Output rise time:
2ns typical
Supply voltage:
5VDC
±
5%
Supply current:
I
CCL
= 50ma typical
I
CCH
= 15ma typical
Operating temperature:
0
°
to 70
°
C
Temp. coefficient of total delay:
100 PPM/
°
C
10%
10%
10%
10%
VCC
GND
IN
T1
T2
T3
T4
T10
Functional diagram for dash numbers < 50
3.5ns
10%
10%
10%
10%
T5
T6
T7
T8
10%
T9
10%
10%
10%
10%
VCC
GND
IN
T1
T2
T3
T4
T10
Functional diagram for dash numbers >= 50
10%
10%
10%
10%
T5
T6
T7
T8
10%
T9
10%
1997 Data Delay Devices
data
delay
devices,
inc.
3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
T2
T4
T6
T8
T10
N/C
GND
VCC
T1
T3
T5
T7
T9
N/C
N/C
14
13
12
11
10
9
8
1
2
3
4
5
6
7
IN
N/C
T2
T4
T6
T8
GND
VCC
T1
T3
T5
T7
T9
T10
DDU7F-xx
DDU7F-xxA2 Gull-Wing
DDU7F-xxB2 J-Lead
DDU7F-xxM
DIP
Military DIP
Military SMD
DDU7F-xxMC3
PIN DESCRIPTIONS
IN
T1-T10 Tap Outputs
VCC
+5 Volts
GND
Ground
Signal Input
DASH NUMBER SPEC.’S
Part
Number
DDU7F-10
DDU7F-20
DDU7F-25
DDU7F-50
DDU7F-100
DDU7F-150
DDU7F-200
DDU7F-250
DDU7F-300
DDU7F-400
DDU7F-500
Total
Delay (ns)
9
±
2.0 *
18
±
2.0 *
22.5
±
2.0 *
50
±
2.5
100
±
5.0
150
±
7.5
200
±
10.0
250
±
12.5
300
±
15.0
400
±
20.0
500
±
25.0
Delay Per
Tap (ns)
1.0
±
0.5
2.0
±
1.0
2.5
±
1.0
5.0
±
2.0
10.0
±
3.0
15.0
±
3.0
20.0
±
3.0
25.0
±
3.0
30.0
±
3.0
40.0
±
4.0
50.0
±
5.0
* Total delay is referenced to first tap
Input to first tap = 3.5ns
±
1ns
NOTE: Any dash number between 10 and
500 not shown is also available.
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相關PDF資料 |
PDF描述 |
|---|---|
| DDU7F-50B2 | Delay Line |
| DDU7F-50M | Delay Line |
| DDU7F-50MC3 | Delay Line |
| DDU7F50ME5 | Logic IC |
| DDU7F-250M | Delay Line |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DDU7F-50B2 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:10-TAP, TTL-INTERFACED FIXED DELAY LINE (SERIES DDU7F) |
| DDU7F-50M | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:10-TAP, TTL-INTERFACED FIXED DELAY LINE (SERIES DDU7F) |
| DDU7F-50MC3 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:10-TAP, TTL-INTERFACED FIXED DELAY LINE (SERIES DDU7F) |
| DDU7F50ME5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| DDU-7J-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tapped Delay Line |
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