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參數資料
| 型號： | DDU8C3-5050 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| 中文描述： | 5，技術咨詢，3.3V CMOS閾值接口固定延遲線 |
| 文件頁數： | 4/4頁 |
| 文件大小： | 45K |
| 代理商： | DDU8C3-5050 |
DDU8C3
Doc #00115
5/19/00
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 www.datadelay.com
4
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (VDD):
3.3V
±
0.1V
Input Pulse:
OUTPUT:
Load:
C
load
:
Threshold:
1 CMOS Gate
5pf
±
10%
1.65V (Rising & Falling)
High = 3.3V
±
0.1V
Low = 0.0V
±
0.1V
50
Max.
3.0 ns Max. (measured
between 0.5V and 2.8V )
PW
IN
= 1.5 x Total Delay
PER
IN
= 10 x Total Delay
Source Impedance:
Rise/Fall Time:
Pulse Width:
Period:
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
T1
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
TIME INTERVAL
COUNTER
PULSE
GENERATOR
COMPUTER
SYSTEM
PRINTER
IN
T2
T3
T4
T5
0.5V
0.5V
Timing Diagram For Testing
T
RISE
T
FALL
PER
IN
PW
IN
T
RISE
T
FALL
2.8V
1.5V
1.5V
1.5V
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
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| DDU8C3-5060 | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5075 | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5100 | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5125 | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| DDU8C3-5060 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5075 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5125 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
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