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參數(shù)資料
| 型號： | DDU8C3-5200 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| 中文描述： | 5，技術(shù)咨詢，3.3V CMOS閾值接口固定延遲線 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 45K |
| 代理商： | DDU8C3-5200 |
DDU8C3
Doc #00115
5/19/00
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
5-TAP, 3.3V CMOS-INTERFACED
FIXED DELAY LINE
(SERIES DDU8C3)
FEATURES
PACKAGES
Five equally spaced outputs
Fits standard 8-pin DIP socket
Low profile
Auto-insertable
Input & outputs fully CMOS interfaced & buffered
10 T
2
L fan-out capability
FUNCTIONAL DESCRIPTION
The DDU8C3-series device is a 5-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
amount determined by the device dash number (See Table). For dash
numbers 5020 and above, the total delay of the line is measured from IN to
T5, and the nominal tap-to-tap delay increment is given by one-fifth of the
total delay. For dash numbers below 5020, the total delay is measured from T1 to T5, and the delay
increment is given by one-fourth of the total delay.
SERIES SPECIFICATIONS
Minimum input pulse width:
40% of total delay
Output rise time:
2ns typical
Supply voltage:
3.3VDC
±
0.3V
Supply current:
I
CCL
= 40
μ
a typical
I
CCH
= 7ma typical
Operating temperature:
-40
°
to 85
°
C
Temp. coefficient of total delay:
300 PPM/
°
C
25%
25%
25%
25%
VDD
GND
IN
T1
T2
T3
T4
T5
Functional diagram for dash numbers < 5020
3.0ns
20%
20%
20%
20%
20%
VDD
GND
IN
T1
T2
T3
T4
T5
Functional diagram for dash numbers >= 5020
2000 Data Delay Devices
data
delay
devices,
inc.
3
8
7
6
5
1
2
3
4
IN
T2
T4
GND
VDD
T1
T3
T5
DDU8C3-xx
DDU8C3-xxA1 Gull-Wing
DIP
PIN DESCRIPTIONS
IN
T1-T5
VDD
GND
Signal Input
Tap Outputs
+3.3 Volts
Ground
DASH NUMBER SPECIFICATIONS
Part
Number
DDU8C3-5004
DDU8C3-5006
DDU8C3-5008
DDU8C3-5010
DDU8C3-5012
DDU8C3-5014
DDU8C3-5020
DDU8C3-5025
DDU8C3-5030
DDU8C3-5035
DDU8C3-5040
DDU8C3-5045
DDU8C3-5050
DDU8C3-5060
DDU8C3-5075
DDU8C3-5100
DDU8C3-5125
DDU8C3-5150
DDU8C3-5175
DDU8C3-5200
DDU8C3-5250
Total
Delay (ns)
4
±
1.0 *
6
±
1.0 *
8
±
2.0 *
10
±
2.0 *
12
±
2.0 *
14
±
2.0 *
20
±
2.0
25
±
2.0
30
±
2.0
35
±
2.0
40
±
2.0
45
±
2.25
50
±
2.5
60
±
3.0
75
±
3.75
100
±
5.0
125
±
6.5
150
±
7.5
175
±
8.0
200
±
10.0
250
±
12.5
Delay Per
Tap (ns)
1.0
±
0.5
1.5
±
0.5
2.0
±
1.0
2.5
±
1.0
3.0
±
1.0
3.5
±
1.0
4.0
±
1.0
5.0
±
1.5
6.0
±
1.5
7.0
±
1.8
8.0
±
2.0
9.0
±
2.0
10.0
±
2.0
12.0
±
2.0
15.0
±
2.5
20.0
±
3.0
25.0
±
3.0
30.0
±
3.0
35.0
±
4.0
40.0
±
4.0
50.0
±
5.0
* Total delay is referenced to first tap output
Input to first tap = 3.0ns
±
1ns
NOTE: Any dash number between 5004 and 5250
not shown is also available.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DDU8C3-5250 | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8F-5035 | 5-TAP, TTL-INTERFACED FIXED DELAY LINE |
| DDU8F-5004A1 | Delay Line |
| DDU8F-5004B1 | Delay Line |
| DDU8F-5004M | Delay Line |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDU8C3-5250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C-5050 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, HCMOS-INTERFACED FIXED DELAY LINE |
| DDU8C-5050A1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| DDU8C-5050B1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| DDU8C-5050M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
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