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參數資料
| 型號： | DEM-ADS1250 |
| 英文描述： | DEM-ADS1250 - Evaluation Fixture |
| 中文描述： | DEM的ADS1250 -評估夾具 |
| 文件頁數： | 3/12頁 |
| 文件大小： | 206K |
| 代理商： | DEM-ADS1250 |
3
DEM-ACF2101BP
V
OUT
= –(i
IN
t)/(C
INT
+ C
EXT
)
V
OUT
= the maximum output voltage (in volts)
C
INT
= the integration capacitor on the chip (in farads)
C
EXT
= the external capacitor, C
2
and C
5
(in farads)
i
IN
= the input current (in amperes)
t = the cycle time (in seconds) see Figure 4
Note that C
can be used alone or in parallel with C
. If
an external integration capacitor is used it should have a low
TECHNICAL DESCRIPTION
ACF2101BP Analog Circuit Configuration
The analog circuit (Figure 2) is designed for simultaneous
two channel operation of the dual ACF2101. Both channels
are configured at the factory for a 0 to 1
μ
A input signal over
a 1ms cycle time. This cycle time and input signal will
provide a 0 to –10V output signal. A block diagram of 1/2
of the ACF2101 is shown in Figure 3. The transfer function
of the ACF2101 can be calculated as:
FIGURE 2. Analog Portion of DEM-ACF2101BP Evaluation Fixture.
C
4
I
J
I
J
C
3
R
4
R
3
1
2
3
4
5
6
7
8
9
1
1
O
G
C
C
I
S
S
I
C
C
G
S
S
S
H
V
V
H
R
S
S
2
2
2
2
2
1
1
1
1
1
1
U
A
O
S
1
1
C
2
C
5
C
9
C
8
C
1
C
1
2
0
2
+
0
H
R
S
1
2
3
4
O
–
+
–
S
8
7
6
5
+
S
O
–
+
U
O
–
+
O
J
O
J
+
–
C
7
C
6
+
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