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參數(shù)資料
| 型號： | DFC10E12S5 |
| 英文描述： | SINGLE OUTPUT |
| 中文描述： | 單輸出 |
| 文件頁數(shù)： | 2/3頁 |
| 文件大小： | 1075K |
| 代理商： | DFC10E12S5 |
2
DFC10 SERIES – SINGLE OUTPUT
NOTES
(1)
All parameters measured at Tc = 25°C, nominal input voltage and full rated load unless otherwise noted.
Refer to the Technical Reference Section for the definition of terms, measurement circuits and other
information.
Noise is measured per Technical Reference Section. Measurement bandwidth is 0-20 MHz for peak-peak
measurements, 10 kHz to 1 MHz for RMS measurements. Output noise is measured with a 0.01μF /
100V ceramic capacitor in parallel with a 1μf / 35V Tantalum capacitor, 1 inch from the output pins to
simulate standard PCB decoupling capacitance.
Short term stability is specified after a 30 minute warmup at full load, constant line and recording the
drift over a 24 hour period.
The input ripple rejection is specified for DC to 120 Hz ripple with a modulation amplitude of 1% of Vin.
(2)
(3)
(4)
DFC10 SERIES APPLICATION NOTES:
External Capacitance Requirements
No external capacitance is required for operation of the DFC10
Series. If a capacitive input source is farther than 1” from the
converter, an additional capacitor may be required at the input pins
for proper operation. This input capacitor should have an ESR
greater than 0.25 ohms. Input capacitors with an ESR less than 0.25
ohms may cause peaking of the input filter and actually degrade
circuit performance.
External output capacitance is not required for operation, however it
is recommended that 1 F to 10 F of tantalum and 0.001 to 0.1 F
ceramic capacitance be selected for reduced system noise. Additional
output capacitance may be added for increased filtering, but should
not exceed 400 F.
Negative Outputs
A negative output voltage may be obtained by connecting the +OUT
to circuit ground and connecting -OUT as the negative output.
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