
4-1
File Number
3117.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 1999
DG201A, DG202
Quad SPST, CMOS Analog Switches
The DG201A and DG202 quad SPST analog switches are
designed using Intersil’s 44V CMOS process. These
bidirectional switches are latch-proof and feature break-
before-make switching. Designed to block signals up to
30V
P-P
in the OFF state, the DG201A and DG202 offer the
advantages of low ON resistance (
≤
175
), wide input signal
range (
±
15V) and provide both TTL and CMOS compatibility.
The DG201A and DG202 are specification and pinout
compatible with the industry standard devices.
Pinout
DG201A, DG202
(CERDIP, PDIP, SOIC)
TOP VIEW
Features
Input Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . .
±
15V
Low r
DS(ON)
(Max). . . . . . . . . . . . . . . . . . . . . . . . . . 175
TTL, CMOS Compatible
Latch-Up Proof
True Second Source
Maximum Supply Ratings. . . . . . . . . . . . . . . . . . . . . . 44V
Logic Inputs Accept Negative Voltages
Functional Block Diagrams
DG201A
DG202
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
DG201AAK
-55 to 125
16 Ld CERDIP
F16.3
DG201ABK
-25 to 85
16 Ld CERDIP
F16.3
DG201ACJ
0 to 70
16 Ld PDIP
E16.3
DG201ACY
0 to 70
16 Ld SOIC
M16.3
DG202AK
-55 to 125
16 Ld CERDIP
F16.3
DG202CJ
0 to 70
16 Ld PDIP
E16.3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN
1
D
1
S
1
V-
GND
S
4
IN
4
D
4
IN
2
S
2
V+ (SUB-
-
NC
S
3
D
3
IN
3
D
2
TRUTH TABLE
LOGIC
0
1
Logic “0”
≤
0.8V, Logic “1”
≥
2.4V
DG201A
ON
OFF
DG202
OFF
ON
IN
1
S
1
D
1
S
2
IN
2
D
2
S
3
IN
3
D
3
S
4
IN
4
D
4
IN
1
S
1
D
1
IN
2
S
2
D
2
S
3
IN
3
D
3
S
4
IN
4
D
4
SWITCHES SHOWN FOR LOGIC “1” INPUT
Data Sheet
June 1999