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參數資料
| 型號： | DG401883 |
| 廠商： | Intersil Corporation |
| 英文描述： | Monolithic CMOS Analog Switches |
| 中文描述： | 單片CMOS模擬開關 |
| 文件頁數： | 4/9頁 |
| 文件大小： | 93K |
| 代理商： | DG401883 |
4
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 16.5V, V- = -16.5V,
V
IN
= 0V or 5V
25
-
0.01
1
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
Full
-
-
5
Negative Supply Current, I-
25
-1
-0.01
-
Full
-5
-
-
Logic Supply Current, I
L
25
-
0.01
1
Full
-
-
5
Ground Current, I
GND
25
-1
-0.01
-
Full
-5
-
-
NOTES:
3. V
IN
= input voltage to perform proper function.
4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, V
IN
= 2.4V, 0.8V (Note 3), V
L
= 5V,
Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITIONS
TEMP
(
o
C)
(NOTE 4)
MIN
(NOTE 5)
TYP
(NOTE 4)
MAX
UNITS
Test Circuits and Waveforms
NOTES:
6. Logic input waveform is inverted for switches that have the
opposite logic sense.
7. V
S
= 10V for t
ON
, V
S
= -10V for t
OFF
.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for IN
2
and S
2
.
For load conditions, see Specifications. C
L
includes fixture and stray
capacitance.
V
O
L
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FIGURE 2A. MEASUREMENT POINTS
C
L
includes fixture and stray capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2. BREAK-BEFORE-MAKE TIME
50%
t
r
< 20ns
t
f
< 20ns
t
OFF
90%
3V
0V
V
S
0V
t
ON
V
O
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
-V
S
SWITCH
INPUT
(NOTE 7)
10%
V
S
R
DS ON
)
---------+
=
SWITCH
INPUT
LOGIC
INPUT
S
1
IN
1
V+
D
1
R
L
C
L
V
O
GND
V-
V
L
0V
-15V
5V
+15V
R
L
= 300
C
L
= 35pF
90%
3V
0V
V
S1
t
D
0V
V
S2
LOGIC
INPUT
SWITCH
OUTPUT
(V
O1
)
SWITCH
OUTPUT
(V
O2
)
90%
t
D
0V
LOGIC
INPUT
V
S1
= 10V
IN
1
V+
D
1
R
L1
C
L1
V
O1
GND
V-
V
L
0V
-15V
5V
+15V
R
L
= 300
C
L
= 35pF
D
2
R
L2
C
L2
V
O2
V
S2
= 10V
DG401, DG403, DG405
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