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參數(shù)資料
| 型號(hào)： | DG526BK |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Analog CMOS Latchable Multiplexers |
| 中文描述： | 16-CHANNEL, SGL ENDED MULTIPLEXER, CDIP28 |
| 封裝： | CERDIP-28 |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大小： | 308K |
| 代理商： | DG526BK |
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12-1
Semiconductor
Features
Direct RESET
TTL and CMOS Compatible Address and Enable
Inputs
Maximum Power Supply Rating . . . . . . . . . . . . . . . .44V
Break-Before-Make Switching
Alternate Source
Applications
Data Acquisition Systems
Communication Systems
Automatic Test Equipment
Microprocessor Controlled Systemd
Description
The DG526, DG527, DG528, and DG529 are CMOS
Monolithic 16-Channel/Dual 4-Channel Analog Multiplexers.
Each device has on-chip address and control latches to sim-
plify design in microprocessor based applications. The DG526
uses 4 address lines to control its 16 channels; the DG527,
DG528 both use 3 address lines to control their 8 channels;
and the DG529 uses 2 address lines to control its 4 channels.
The enable pin is used to enable the address latches during
the WR pulse. It can be hard wired to the logic supply if one of
the channels will always be used (except during a reset) or it
can be tied to address decoding circuitry for memory mapped
operation. The RS pin is used to clear all latches regardless of
the state of any other latch or control line. The WR pin is used
to transfer the state of the address control lines to their
latches, except during a reset or when EN is low.
A channel in the ON state conducts signals equally well in
both directions. In the OFF state each channel blocks volt-
ages up to the supply rails. The address inputs, WR, RS and
the enable input are TTL and CMOS compatible over the full
specified operation temperature range.
Part Number Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
DG526AK
-55 to 125
28 Ld CERDIP
F28.6
DG526AK/883B
-55 to 125
28 Ld CERDIP
F28.6
DG526BK
-25 to 85
28 Ld CERDIP
F28.6
DG526BY
-25 to 85
28 Ld SOIC
M28.3
DG526CJ
0 to 70
28 Ld PDIP
E28.6
DG526CK
0 to 70
28 Ld CERDIP
F28.6
DG526CY
0 to 70
28 Ld SOIC
M28.3
DG527AK
-55 to 125
28 Ld CERDIP
F28.6
DG527AK/883B
-55 to 125
28 Ld CERDIP
F28.6
DG527BK
-25 to 85
28 Ld CERDIP
F28.6
DG527BY
-25 to 85
28 Ld SOIC
M28.3
DG527CJ
0 to 70
28 Ld PDIP
E28.6
DG527CK
0 to 70
28 Ld CERDIP
F28.6
DG527CY
0 to 70
28 Ld SOIC
M28.3
DG528AK
-55 to 125
18 Ld CERDIP
F18.3
DG528AK/883B
-55 to 125
18 Ld CERDIP
F18.3
DG528BK
-25 to 85
18 Ld CERDIP
F18.3
DG528BY
-25 to 85
18 Ld SOIC
M18.3
DG528CJ
0 to 70
18 Ld PDIP
E18.3
DG528CK
0 to 70
18 Ld CERDIP
F18.3
DG528CY
0 to 70
18 Ld SOIC
M18.3
DG529AK
-55 to 125
18 Ld CERDIP
F18.3
DG529AK/883B
-55 to 125
18 Ld CERDIP
F18.3
DG529BK
-25 to 85
18 Ld CERDIP
F18.3
DG529BY
-25 to 85
18 Ld SOIC
M18.3
DG529CJ
0 to 70
18 Ld PDIP
E18.3
DG529CK
0 to 70
18 Ld CERDIP
F18.3
DG529CY
0 to 70
18 Ld SOIC
M18.3
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
April 1999
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1999
DG526, DG527,
DG528, DG529
Analog CMOS
Latchable Multiplexers
File Number
3139.2
FOR A POSSIBLE SUBSTITUTE PRODUCT
call Central Applications 1-800-442-7747
or email: centapp@harris.com
OBSOLETE PRODUCT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DG526BY | Analog CMOS Latchable Multiplexers |
| DG526CJ | Analog CMOS Latchable Multiplexers |
| DG526CK | Analog CMOS Latchable Multiplexers |
| DG526CY | Analog CMOS Latchable Multiplexers |
| DG527 | Analog CMOS Latchable Multiplexers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DG526BY | 制造商:Harris Corporation 功能描述: |
| DG526BY WAF | 制造商:Harris Corporation 功能描述: |
| DG526CJ | 制造商:Rochester Electronics LLC 功能描述:28 PDIP 0+70 15.0V 16-CHANNEL LATCHABLE CMOS ANALOG MUX - Bulk |
| DG526CK | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DG526CY | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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