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參數(shù)資料
| 型號： | DIR1703E |
| 英文描述： | DIGITAL AUDIO INTERFACE RECEIVER |
| 中文描述： | 數(shù)字音頻接口接收機 |
| 文件頁數(shù)： | 9/19頁 |
| 文件大小： | 236K |
| 代理商： | DIR1703E |
SLES007
–
JULY 2001
9
www.ti.com
system clock output (continued)
Table 5. System Clock Operation Mode
CONDITIONS
CLOCK AND DATA OUTPUTS
MODE
CKSEL
S/PDIF
DATA
SCKO
BCKO
LRCKO
DOUT
BRATE
UNLOCK
CS. UR
BIT
AD.
EMFLG
After
RESET
Default PLL
(128, 256, 384, 512
fS)
PLL
(128, 256, 384, 512
fS)
HOLD
(128, 256, 384, 512
fS)
Crystal
(128, 256, 384, 512
fS)
Crystal
(128, 256, 384, 512
fS)
Crystal
(128, 256, 384, 512
fS)
Default
PLL
(64 fS)
Default
PLL
(1 fS)
MUTE
LOW
HIGH
LOW
LOW
PLL
LOW
YES
PLL
(64 fS)
PLL
(1 fS)
DATA
DETECT
LOW
DATA
DATA
NO
HOLD
(64 fS)
HOLD
(1 fS)
MUTE
HOLD
HIGH
Unknown
HOLD
After
RESET
Crystal
(64 fS)
Crystal
(1 fS)
MUTE
LOW
HIGH
LOW
LOW
CRYSTAL
HIGH
YES
Crystal
(64 fS)
Crystal
(1 fS)
MUTE
DETECT
LOW
Unknown
LOW
NO
Crystal
(64 fS)
Crystal
(1 fS)
MUTE
Unknown
HIGH
Unknown
LOW
In the PLL mode, the DIR1703 will be the same frequencies as the crystal mode after RESET; however, the frequency error is below 1%.
Holds the latest tracked frequency.
SCKO timing
L
H
0.8 V
2 V
System Clock Pulse
Cycle Time
tSCKH
tSCKL
SCKO
SCKO Clock Pulse Width High
SCKO Clock Pulse Width Low
1/128 fS, 1/256 fS, 1/384 fS or 1/512 fS.
tSCKH
tSCKL
7 ns (min)
7 ns (min)
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PDF描述 |
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| DISADVANTAGE | Disadvantage of On-Chip Transient Protection (105k) |
| DISCONTINUEDPRODUCTS | Discontinued Products - August 2. 1999 |
| DISPLAY-XREF | Optoelectronic |
| DIV100 | DIV100 - DISCONTINUED PRODUCT. No longer recommended for new design. |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DIR1703E/2K | 制造商:Texas Instruments 功能描述:Audio Interface Receiver 28-Pin SSOP T/R 制造商:Texas Instruments 功能描述:AUD INTRFC RCVR 28SSOP - Tape and Reel |
| DIR-600/E | 制造商:D-Link Networks 功能描述: |
| DIR-605L/E | 制造商:D-Link Networks 功能描述: |
| DIR-615/E | 制造商:D-Link Networks 功能描述: |
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