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參數(shù)資料
| 型號： | DJCE6353882077 |
| 廠商： | INTEL CORP |
| 元件分類： | 接收器 |
| 英文描述： | Nordig Unified DVB-T COFDM Terrestrial Demodulator for PC-TV and Hand-held Digital TV (DTV) |
| 中文描述： | VIDEO DISCRIMINATOR, QFP64 |
| 封裝： | LQFP-64 |
| 文件頁數(shù)： | 24/26頁 |
| 文件大小： | 322K |
| 代理商： | DJCE6353882077 |
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CE6353
Data Sheet
24
Intel Corporation
4.4.1.3 Calculating Crystal Power Dissipation
To calculate the power dissipated in a crystal the following equation can be used.
Equation 3 -
Pc
= power dissipated in crystal at resonant frequency (W)
Vpp
= maximum peak to peak output swing of amplifier is 1.8 V for all CVDD
Zin
= crystal network impedance (see Equation 2)
4.4.1.4 Capacitor Values
Using the loop gain limits (5 < A < 25), the maximum and minimum values for C1 and C2 can be calculated with
Equation 4 below.
Equation 4 -
Note: Equation 4 was derived from Equation 1 and Equation 2 using the premise that C1 = C2.
Within these limits, any value for C1 and C2 can now be selected. Normally C1 and C2 are chosen such that the
resulting crystal load capacitance C
L
(see Equation 5) is close to the crystal manufacturers recommended C
L
(standard values for C
L
are 15 pF, 20 pF and 30 pF). The crystal will then operate very near its specified frequency.
Equation 5 -
C
par12
=
parasitic capacitance between the XTI and XTO pins. It consists of the IC package’s pin-to-pin
capacitance (including any socket used) and the printed circuit board’s track-to-track capacitance.
C
par12
≈
2pF.
If some frequency pulling can be tolerated, a crystal load capacitance different from the crystal manufacturer’s
recommended C
L
may be acceptable. Larger values of C
L
tend to reduce the influence of circuit variations and
tolerances on frequency stability. Smaller values of C
L
tend to reduce startup time and crystal power dissipation.
Care must however be taken that C
L
does not fall outside the crystal pulling range or the circuit may fail to start up
altogether. It is also possible to quote C
L
to the crystal manufacturer who can then cut a crystal to order which will
resonate, under the specified load conditions, at the desired frequency.
Finally the power dissipation in the crystal must be checked. If Pc is too high C1 and C2 must be reduced. If this is
not feasible C2 alone may be reduced. Unbalancing C1 and C2 will, however, require checking if the loop gain
condition is still satisfied. This must be done using Equation 1.
C
2
C
1
P
c
= 8.Z
in
V
pp2
C
in
= C
out
=
g
m
A
2
R
f
1
Z
o
1
(2.
π
.f)
2
.ESR when: C
1
= C
2
= C
out
- C
par
-
-
.
- C
L
= C
out
. C
in
C
out
+ C
in
+ C
par12
Note:
2 >
> 0.5
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