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參數資料
| 型號： | DJIXE972MCCA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 48/92頁 |
| 文件大小： | 666K |
| 代理商： | DJIXE972MCCA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
48
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
5.7.3.2
Physical Medium Attachment Sublayer
5.7.3.2.1
Link
In 100 Mbps mode, link is established when the descrambler becomes locked and remains locked
for approximately 50 ms. Link remains up unless the descrambler receives less than 16 consecutive
idle symbols in any 2 ms period. This operation filters out small noise hits that may disrupt the link.
In 100 Mbps mode, link is established when the descrambler becomes locked and remains locked
for approximately 50 ms. Link remains up unless the descrambler receives less than 16 consecutive
idle symbols in any 2 ms period. This operation filters out small noise hits that may disrupt the link.
For short periods, MLT-3 idle waveforms meet all criteria for 10BASE-T start delimiters. A
working 10BASE-T receive may temporarily indicate link to 100BASE-TX waveforms. However,
the PHY does not bring up a permanent 10 Mbps link.
The LXT972M Transceiver reports link failure through the MII status bits (Register bits 1.2 and
17.10). Link failure causes the LXT972M Transceiver to re-negotiate if auto-negotiation is
enabled.
5.7.3.2.2
Link Failure Override
The LXT972M Transceiver normally transmits data packets only if it detects the link is up. Setting
Register bit 16.14 = 1 overrides this function, allowing the LXT972M Transceiver to transmit data
packets even when the link is down. This feature is provided as a transmit diagnostic tool.
Note:
Auto-negotiation must be disabled to transmit data packets in the absence of link. If auto-
negotiation is enabled, the LXT972M Transceiver automatically transmits FLP bursts if the link is
down.
Caution:
During normal operation, Intel does not recommend setting Register bit 16.14 for 100 Mbps
receive functions because receive errors may be generated.
5.7.3.2.3
Carrier Sense
For 100BASE-TX links, a start-of-stream delimiter (SSD) or /J/K symbol pair causes assertion of
carrier sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair causes de-assertion of
CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R. However, in
this case RX_ER is asserted for one clock cycle when CRS is de-asserted.
Intel does not recommend using CRS for Interframe Gap (IFG) timing for the following reasons:
CRS de-assertion time is slightly longer than CRS assertion time. As a result, an IFG interval
appears somewhat shorter to the MAC than it actually is on the wire.
CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half-
duplex mode.
5.7.3.2.4
Receive Data Valid
The LXT972M Transceiver asserts RX_DV to indicate that the received data maps to valid
symbols. In 100 Mbps operation, RX_DV is active with the first nibble of preamble.
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| DJIXE972MCEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MEAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MECA4 | Single-Port 10/100 Mbps PHY Transceiver |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| DJIXE972MCEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MEAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MECA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MEEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MHAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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