- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376726 > DJIXE972MCEA4 (Intel Corp.) Single-Port 10/100 Mbps PHY Transceiver PDF資料下載
參數(shù)資料
| 型號： | DJIXE972MCEA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁數(shù)： | 19/92頁 |
| 文件大小： | 666K |
| 代理商： | DJIXE972MCEA4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
19
Table 9
lists signal descriptions of the LXT972M Transceiver power, ground, and no-connect pins.
Table 10
lists signal descriptions of LXT972M Transceiver Joint Test Action Group (JTAG) pins.
Note:
If a JTAG port is not used, these pins do not need to be terminated.
Table 9. Intel
LXT972M Transceiver Power, Ground, No-Connect Signal Descriptions
LQFP
Pin#
Symbol
Type
Signal Description
13
GNDA
–
Analog Ground.
5, 9, 24,
25, 30,
38
GND
–
Ground Input/Output.
Ground return for digital I/O circuits (VCCIO).
6, 29
VCCIO
–
MII Power.
Requires either a 3.3 V or a 2.5 V supply. Must be supplied
from the same source used to power the MAC on the other
side of the MII.
For the LXT972M Transceiver, VCCIO is 3.3 V.
16
VCCA
–
Analog Power.
Requires a 3.3 V power supply.
39
VCCD
–
Digital Power.
Requires a 3.3 V power supply.
7, 8
NC
–
No Connection
.
These pins are not used and must not be terminated.
Table 10. Intel
LXT972M Transceiver JTAG Test Signal Descriptions
LQFP
Pin#
Symbol
Type
Signal Description
19
TDI
I
Test Data Input
.
Test data sampled with respect to the rising edge of TCK.
20
TDO
O
Test Data Output
.
Test data driven with respect to the falling edge of TCK.
21
TMS
I
Test Mode Select
.
22
TCK
I
Test Clock
.
Clock input for boundary scan.
23
TRST_L
I
Test Reset
.
This active-low test reset input is sourced by ATE.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXE972MEAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MECA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MEEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MHAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MHCA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXE972MEAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MECA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MEEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MHAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MHCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。