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參數資料
| 型號： | DJIXE972MKAA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 35/92頁 |
| 文件大小： | 666K |
| 代理商： | DJIXE972MKAA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
35
5.5.1.2
Manual Next Page Exchange
“Next Page Exchange” information is additional information that exceeds the information required
by Base Page exchange and that is sent by “Next Pages”. The LXT972M Transceiver fully
supports the IEEE 802.3 standard method of negotiation through the Next Page exchange.
The Next Page exchange uses Register 7 to send information and Register 8 to receive it. Next
Page exchange occurs only if both ends of the link partners advertise their ability to exchange Next
Pages. Register bit 6.1 is used to make manual next page exchange easier for software. This
register bit is cleared when a new negotiation occurs, preventing the user from reading an old value
in Register 6 and assuming there is valid information in Registers 5 and 8.
5.5.1.3
Controlling Auto-Negotiation
When auto-negotiation is controlled by software, Intel recommends the following steps:
1. After power-up, power-down, or reset, the power-down recovery time
(specified in
Table 39,
“Intel LXT972M Transceiver RESET_L Pulse Width and Recovery Timing” on page 74
)
must be exhausted before proceeding.
2. Set the Auto-Negotiation Advertisement Register bits in Register 4 as desired.
3. Enable auto-negotiation. (Set MDIO Register bit 0.12 = 1.)
4. To ensure proper operation, enable or restart auto-negotiation as soon as possible after writing
to Register 4.
5.5.2
Parallel Detection
In parallel with auto-negotiation, the LXT972M Transceiver also monitors for 10 Mbps Normal
Link Pulses (NLP) or 100 Mbps Idle symbols. If either symbol is detected, the device
automatically reverts to the corresponding speed in half-duplex mode. Parallel detection allows the
LXT972M Transceiver to communicate with devices that do not support auto-negotiation.
When parallel detection resolves a link, the link must be established in half-duplex mode.
According to IEEE standards, the forced link partner cannot be configured to full-duplex. If the
auto-negotiation link partner does not advertise half-duplex capability at the speed of the forced
link partner, link is not established. The IEEE Standard prevents full-duplex-to-half-duplex link
connections.
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PDF描述 |
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| DJIXE972MKCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MKEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MLAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MLCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MLCA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DJIXE972MKCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MKEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MLAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MLCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MLEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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