- 您現在的位置：買賣IC網 > PDF目錄376726 > DJIXE972MKEA4 (Intel Corp.) Single-Port 10/100 Mbps PHY Transceiver PDF資料下載
參數資料
| 型號： | DJIXE972MKEA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 34/92頁 |
| 文件大小： | 666K |
| 代理商： | DJIXE972MKEA4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
34
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
5.5
Establishing Link
Figure 6
shows an overview of link establishment for the LXT972M Transceiver.
Note:
When a link is established by parallel detection, the LXT972M Transceiver sets the duplex mode to
half-duplex, as defined by the IEEE 802.3 standard.
5.5.1
Auto-Negotiation
If not configured for forced operation, the LXT972M Transceiver attempts to auto-negotiate with
its link partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of up to 33 link pulses
spaced 62.5
μ
s apart. Odd link pulses (clock pulses) are always present. Even link pulses (data
pulses) may be absent or present to indicate a ‘0’ or a ‘1’. Each FLP burst exchanges 16 bits of
data, which are referred to as a “link code word”. All devices that support auto-negotiation must
implement the “Base Page” defined by the IEEE 802.3 standard (Registers 4 and 5).
The LXT972M Transceiver also supports the optional “Next Page” function as listed in
Table 48,
“Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7” on page 82
and
Table 49,
“Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8” on page 82
.
5.5.1.1
Base Page Exchange
By exchanging Base Pages, the LXT972M Transceiver and its link partner communicate their
capabilities to each other. Both sides must receive at least three consecutive identical base pages for
negotiation to continue. Each side identifies the highest common capabilities that both sides
support, and each side configures itself accordingly.
Figure 6. Link Establishment Overview)
Check Value
0.12
Start
Done
Enable
Auto-Neg/Parallel Detection
Go To Forced
Settings
Attempt Auto-
Negotiation
Listen for 10T
Link Pulses
Listen for 100TX
Idle Symbols
Link Up
NO
YES
Power-Up, Reset,
or Link Failure
Disable
Auto-Negotiation
0.12 = 0
0.12 = 1
B3496-01
相關PDF資料 |
PDF描述 |
|---|---|
| DJIXE972MLAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MLCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MLCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MLEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MNAA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DJIXE972MLAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MLCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MLEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MNAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MNCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
發布緊急采購，3分鐘左右您將得到回復。