- 您現在的位置：買賣IC網 > PDF目錄376726 > DJIXE972MLCA4 (Intel Corp.) Single-Port 10/100 Mbps PHY Transceiver PDF資料下載
參數資料
| 型號： | DJIXE972MLCA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 46/92頁 |
| 文件大小： | 666K |
| 代理商： | DJIXE972MLCA4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁當前第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
46
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
5.7.3.1
Physical Coding Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/
decoding function.
For 100BASE-TX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver
as long as TX_EN is de-asserted.
5.7.3.1.1
Preamble Handling
When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start-of-
Stream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues
to encode the remaining MII data, following the 4B/5B coding in
Table 15
, until TX_EN is de-
asserted. It then returns to supplying IDLE symbols to the line driver.
In the receive direction, the PCS layer performs the opposite function, substituting two preamble
nibbles for the SSD. In 100 Mbps operation, preamble is always passed through the PCS layer to
the MII interface.
Table 15. 4B/5B Coding (Sheet 1 of 2)
Code Type
4B Code
3 2 1 0
Name
5B Code
4 3 2 1 0
Interpretation
DATA
0 0 0 0
0
1 1 1 1 0
Data 0
0 0 0 1
1
0 1 0 0 1
Data 1
0 0 1 0
2
1 0 1 0 0
Data 2
0 0 1 1
3
1 0 1 0 1
Data 3
0 1 0 0
4
0 1 0 1 0
Data 4
0 1 0 1
5
0 1 0 1 1
Data 5
0 1 1 0
6
0 1 1 1 0
Data 6
0 1 1 1
7
0 1 1 1 1
Data 7
1 0 0 0
8
1 0 0 1 0
Data 8
1 0 0 1
9
1 0 0 1 1
Data 9
1 0 1 0
A
1 0 1 1 0
Data A
1 0 1 1
B
1 0 1 1 1
Data B
1 1 0 0
C
1 1 0 1 0
Data C
1 1 0 1
D
1 1 0 1 1
Data D
1 1 1 0
E
1 1 1 0 0
Data E
1 1 1 1
F
1 1 1 0 1
Data F
IDLE
undefined
I
1
1 1 1 11
Used as inter-stream fill code
1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs, and /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs, and /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.
相關PDF資料 |
PDF描述 |
|---|---|
| DJIXF972MLCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MLEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MNAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MNCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MNEA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DJIXE972MLEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MNAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MNCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MNEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MPAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
發布緊急采購，3分鐘左右您將得到回復。