欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: DJIXP972MKAA4
廠商: Intel Corp.
英文描述: Single-Port 10/100 Mbps PHY Transceiver
中文描述: 單端口10/100 Mbps的物理層收發器
文件頁數: 25/92頁
文件大小: 666K
代理商: DJIXP972MKAA4
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
25
5.2.2
MII Data Interface
The LXT972M Transceiver supports a standard Media Independent Interface (MII). The MII
consists of a data interface and a management interface. The MII Data Interface passes data
between the LXT972M Transceiver and a Media Access Controller (MAC). Separate parallel buses
are provided for transmit and receive. This interface operates at either 10 Mbps or 100 Mbps. The
speed is set automatically, once the operating conditions of the network link have been determined.
For details, see
Section 5.6, “MII Operation” on page 36
.
Increased MII Drive Strength.
A higher Media Independent Interface (MII) drive strength may
be desired in some designs to drive signals over longer PCB trace lengths, or over high-capacitive
loads, through multiple vias, or through a connector. The MII drive strength in the LXT972M
Transceiver can be increased by setting Register bit 26.11 through software control. Setting
Register bit 26.11 = 1 through the MDC/MDIO interface sets the MII pins (RXD[3:0], RX_DV,
RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a higher drive strength.
5.2.3
Configuration Management Interface
The LXT972M Transceiver provides both an MDIO interface and a reduced hardware control
interface for device configuration and management.
5.2.3.1
MDIO Management Interface
MDIO management interface topics include the following:
Section 5.2.3.1.1, “MDIO Addressing for Intel LXT972M Transceiver”
Section 5.2.3.1.2, “MDIO Frame Structure”
The LXT972M Transceiver supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT972M Transceiver. The MDIO interface consists of a
physical connection, a specific protocol that runs across the connection, and an internal set of
addressable registers.
Some registers are required and their functions are defined by the IEEE 802.3 standard. The
LXT972M Transceiver also supports additional registers for expanded functionality. The
LXT972M Transceiver supports multiple internal registers, each of which is 16 bits wide. Specific
register bits are referenced using an “X.Y” notation, where X is the register number (0-31) and Y is
the bit number (0-15).
5.2.3.1.1
MDIO Addressing for Intel
LXT972M Transceiver
The MDIO addressing protocol allows a controller to communicate with multiple LXT972M
Transceivers.As listed in
Table 12
, pins ADDR[1:0] determine the PHY device address that is
selected.
相關PDF資料
PDF描述
DJIXP972MKCA4 Single-Port 10/100 Mbps PHY Transceiver
DJIXP972MKEA4 Single-Port 10/100 Mbps PHY Transceiver
DJLXT972MKCA4 Single-Port 10/100 Mbps PHY Transceiver
DJLXT972MKEA4 Single-Port 10/100 Mbps PHY Transceiver
DJLXT972MLAA4 Single-Port 10/100 Mbps PHY Transceiver
相關代理商/技術參數
參數描述
DJIXP972MKCA4 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver
DJIXP972MKEA4 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver
DJIXP972MLAA4 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver
DJIXP972MLCA4 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver
DJIXP972MLEA4 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver
主站蜘蛛池模板: 平谷区| 尼木县| 扎鲁特旗| 绵竹市| 蒙阴县| 罗源县| 西吉县| 遂宁市| 尚义县| 泊头市| 漳州市| 宿州市| 九龙县| 抚顺县| 治县。| 淮南市| 会理县| 贡觉县| 海兴县| 昔阳县| 宜都市| 望都县| 平潭县| 四平市| 射洪县| 吉木乃县| 福州市| 寻乌县| 海口市| 孝感市| 兖州市| 栖霞市| 瓦房店市| 宾阳县| 朔州市| 玛多县| 南陵县| 元氏县| 巫山县| 乌兰察布市| 来安县|