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參數資料
| 型號： | DJLXT972MKCA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 31/92頁 |
| 文件大?。?/td> | 666K |
| 代理商： | DJLXT972MKCA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
31
5.4.1
MDIO Control Mode and Hardware Control Mode
In the MDIO Control mode, the LXT972M Transceiver reads the Hardware Control Interface pins
to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control
reverts to the MDIO interface.
The following modes are available using MDIO Control.
Force network link operation to:
— 100BASE-TX, Full-Duplex
— 100BASE-TX, Half-Duplex
— 10BASE-T, Full-Duplex
— 10BASE-T, Half-Duplex
Allow auto-negotiation/parallel-detection
On power-up or hardware reset, the LXT972M Transceiver reads the Hardware Control Interface
pins and sets the MDIO registers accordingly.
The following modes are available using the Hardware Control:
Auto-negotiation-enabled advertising, either:
— 10/100 BASE-T Full/Half Duplex
— 10/100 BASE-T Half Duplex
LXT972M Transceiver device ID enable
Link Hold-off
When the network link is forced to a specific configuration, the LXT972M Transceiver
immediately begins operating the network interface as commanded. When auto-negotiation is
enabled, the LXT972MTransceiver begins the auto-negotiation/parallel-detection operation.
5.4.2
Reduced-Power Modes
This section discusses the LXT972M Transceiver reduced-power modes.
5.4.2.1
Software Power Down
Software power-down control is provided by Register bit 0.11 in the Control Register. (See
Table 41 on page 76.)
During soft power-down, the following conditions are true:
The network port is shut down.
The MDIO registers remain accessible.
5.4.3
Reset for Intel
LXT972M Transceiver
The LXT972M Transceiver provides both hardware and software resets, each of which manage
differently the configuration control of auto-negotiation, speed, and duplex-mode selection.
For a software reset, Register bit 0.15 = 1. For register bit definitions used for software reset, see
Table 41, “Control Register - Address 0, Hex 0” on page 76
.
相關PDF資料 |
PDF描述 |
|---|---|
| DJLXT972MKEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MLAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MLCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MLEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MNAA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DJLXT972MKEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MLAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MLC.A4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MLCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MLEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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