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參數資料
| 型號： | DJLXT972MPAA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 77/92頁 |
| 文件大小： | 666K |
| 代理商： | DJLXT972MPAA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
77
Table 42
lists MII status register bits.
Table 42. MII Status Register #1 - Address 1, Hex 1
Bit
Name
Description
Type
1
Default
1.15
100BASE-T4
Not Supported
0 = PHY not able to perform 100BASE-T4
1 = PHY able to perform 100BASE-T4
RO
0
1.14
100BASE-X Full-Duplex
0 = PHY not able to perform full-duplex 100BASE-X
1 = PHY able to perform full-duplex 100BASE-X
RO
1
1.13
100BASE-X Half-Duplex
0 = PHY not able to perform half-duplex
100BASE-X
1 = PHY able to perform half-duplex 100BASE-X
RO
1
1.12
10 Mbps Full-Duplex
0 = PHY not able to operate at 10 Mbps full-duplex
mode
1 = PHY able to operate at 10 Mbps in full-duplex
mode
RO
1
1.11
10 Mbps Half-Duplex
0 = PHY not able to operate at 10 Mbps in half-
duplex
1 = PHY able to operate at 10 Mbps in half-duplex
mode
RO
1
1.10
100BASE-T2 Full-
Duplex
Not Supported
0 = PHY not able to perform full-duplex
100BASE-T2
1 = PHY able to perform full-duplex 100BASE-T2
RO
0
1.9
100BASE-T2 Half-
Duplex
Not Supported
0 = PHY not able to perform half-duplex
100BASE-T2
1 = PHY able to perform half-duplex 100BASE-T2
RO
0
1.8
Extended Status
0 = No extended status information in register 15
1 = Extended status information in register 15
RO
0
1.7
Reserved
Ignore when read.
RO
0
1.6
MF Preamble
Suppression
0 = PHY cannot accept management frames with
preamble suppressed
1 = PHY accepts management frames with
preamble suppressed
RO
0
1.5
Auto-Negotiation
complete
0 = Auto-negotiation not complete
1 = Auto-negotiation complete
RO
0
1.4
Remote Fault
0 = No remote fault condition detected
1 = Remote fault condition detected
RO/LH
0
1.3
Auto-Negotiation Ability
0 = PHY is not able to perform auto-negotiation
1 = PHY is able to perform auto-negotiation
RO
1
1.2
Link Status
0 = Link is down
1 = Link is up
RO/LL
0
1.1
Jabber Detect
0 = Jabber condition not detected
1 = Jabber condition detected
RO/LH
0
1.0
Extended Capability
0 = Basic register capabilities
1 = Extended register capabilities
RO
1
1. RO = Read Only
LL = Latching Low
LH = Latching High
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|---|---|
| DJLXT972MPCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MPEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MQAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MQCA4 | Single-Port 10/100 Mbps PHY Transceiver |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| DJLXT972MPCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MPEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MQAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MQCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MQEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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