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參數資料
| 型號： | DJLXT972MTCA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 8/92頁 |
| 文件大小： | 666K |
| 代理商： | DJLXT972MTCA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
8
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
75
Chapter 8.0, “Register Definitions - IEEE Base Registers”
-
Table 40 “Register Set for IEEE Base Registers”
changed.
-
Table 41 “Control Register - Address 0, Hex 0”
changed.
83
Chapter 9.0, “Register Definitions - Product-Specific Registers”
.
-
Table 50 “Register Set for Product-Specific Registers”
changed.
-
Table 54 “LED Configuration Register - Address 20, Hex 14”
changed.
-
Table 56 “Transmit Control Register - Address 30, Hex 1E”
90
Chapter 10.0, “Intel LXT972M Transceiver Package Specifications”
.
-
Figure 35 “Intel LXT972M Transceiver LQFP Package Specifications”
changed.
Intel
LXT972M Transceiver Datasheet Revision 002
Revision Date: July 14, 2004
Page
Description
1
Text changed.
Figure 1 “Intel
LXT972M Transceiver Block Diagram”
- Deleted ECL Driver from figure.
10
21
Section 5.1, “Introduction”
- Text changed.
22
Section 5.2.1.1, “Twisted-Pair Interface”
- Added text on MDI crossover.
23
Section 5.2.1.2, “Fault Detection and Reporting”
- Text changed.
26
Section 5.3.2.1, “External Crystal/Oscillator”
- Text changed.
Table 12 “Hardware Configuration Settings for Intel
LXT972M Transceiver”
- Bit value for 0.8
changed.
30
33
Section 5.5.2, “Parallel Detection”
- Text changed.
36
Section 5.6.2, “Transmit Enable”
- Text changed.
37
Section 5.6.4, “Carrier Sense”
- Text changed.
45
Section 5.7.3.1.1, “Preamble Handling”
- Text changed.
47
Section 5.7.3.2.1, “Link”
- Added text.
47
Section 5.7.3.2.2, “Link Failure Override”
- Added text.
47
Section 5.7.3.2.4, “Receive Data Valid”
- Text changed.
48
Section 5.7.3.3.2, “Polarity Correction”
- Text changed.
53
Section 5.9.4, “LED Pulse Stretching”
- Text changed.
80
Table 46 “Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7”
- Bits 7.10:0 and 7.13
changed.
80
Table 47 “Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8”
- Bits
8.18 and 8.10:0 changed.
85
Table 52 “LED Configuration Register - Address 20, Hex 14”
- Bit 20.0 changed.
Intel
LXT972M Transceiver Datasheet Revision 001
Revision Date: July 2, 2004
Page
Description
-
Initial release of this document.
Intel
LXT972M Transceiver Datasheet Revision 003
Revision Date: October 21, 2004
Page
Description
相關PDF資料 |
PDF描述 |
|---|---|
| DJLXT972MTEA4 | Single-Port 10/100 Mbps PHY Transceiver |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| DJLXT972MTEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXTEAD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJLXTEAD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJLXTEAD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJLXTEAD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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