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參數資料
| 型號： | DJLXT972MTEA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 37/92頁 |
| 文件大小： | 666K |
| 代理商： | DJLXT972MTEA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
37
5.6.1
MII Clocks
The LXT972M Transceiver is the master clock source for data transmission, and it supplies both
MII clocks (RX_CLK and TX_CLK). It automatically sets the clock speeds to match link
conditions.
When the link is operating at 100 Mbps, the clocks are set to 25 MHz.
When the link is operating at 10 Mbps, the clocks are set to 2.5 MHz.
Figure 7
through
Figure 9
show the clock cycles for each mode.
Note:
The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The
LXT972M Transceiver samples these signals on the rising edge of TX_CLK.
Figure 7. Clocking for 10BASE-T
Figure 8. Clocking for 100BASE-X
RX_CLK
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
TX_CLK
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
Constant 25 MHz
XI
B3390-01
RX_CLK
2.5 MHz during auto-negotiation
TX_CLK
Constant 25 MHz
XI
25 MHz once 100BASE-X
Link Established
2.5 MHz during auto-negotiation
25 MHz once 100BASE-X
Link Established
B3391-01
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| DJLXTEAD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJLXTECD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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