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參數(shù)資料
型號: DLO32F-9D1
英文描述: Crystal Oscillator
中文描述: 晶體振蕩器
文件頁數(shù): 2/4頁
文件大小: 75K
代理商: DLO32F-9D1
DLO32F
Doc #98002
3/17/98
DATA DELAY DEVICES, INC.
2
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
This Material Copyrighted by Its Respective Manufacturer
APPLICATION NOTES
THERMAL STABILITY
The delay line used internally to develop the clock
signals in the DLO32F has a thermal coefficient
of 100ppm/C. For low frequency units, this is also
the thermal coefficient of the output frequency.
For higher frequency units, however, other
internal effects must be considered, and the
actual thermal coefficient may be somewhat
higher.
POWER SUPPLY BYPASSING
The DLO32F relies on a stable power supply to
produce a repeatable frequency within the stated
tolerances. A 0.1uf capacitor from VCC to GND,
located as close as possible to the VCC pin, is
recommended. A wide VCC trace and a clean
ground plane should be used.
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
V
CC
V
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-55
MAX
7.0
V
DD
+0.3
150
300
UNITS
V
V
C
C
NOTES
10 sec
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
High Level Output Voltage
SYMBOL
V
OH
MIN
2.5
TYP
3.4
MAX
UNITS
V
NOTES
V
CC
= MIN, I
OH
= MAX
V
IH
= MIN, V
IL
= MAX
V
CC
= MIN, I
OL
= MAX
V
IH
= MIN, V
IL
= MAX
Low Level Output Voltage
V
OL
0.35
0.5
V
High Level Output Current
Low Level Output Current
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current at Maximum
Input Voltage
High Level Input Current
Low Level Input Current
Short-circuit Output Current
Output High Fan-out
Output Low Fan-out
I
OH
I
OL
V
IH
V
IL
V
IK
I
IHH
-1.0
20.0
mA
mA
V
V
V
mA
2.0
0.8
-1.2
0.1
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
I
IH
I
IL
I
OS
20
-0.6
-150
25
12.5
μ
A
mA
mA
Unit
Load
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
-60
TABLE 3: AC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
Enable to Clock On (Inherent Delay)
Disable to Clock Off
Clock Skew
Gate Recovery Time
SYMBOL
t
EO
t
DO
t
CS
t
GR
MIN
1.5
1.5
1.5
50
TYP
3.0
2.5
2.5
MAX
4.5
3.5
3.5
UNITS
ns
ns
ns
% of Clock Period
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