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參數資料
| 型號： | DM2203TME-20 |
| 英文描述： | Enhanced DRAM (EDRAM) |
| 中文描述： | 增強的DRAM（eDRAM內存） |
| 文件頁數： | 1/21頁 |
| 文件大?。?/td> | 124K |
| 代理商： | DM2203TME-20 |
DM2203/2213 Mutibank EDOEDRAM
512Kbx 8 EnhancedDynamc RAM
ProductSpecifcaton
1996 Enhanced Memory Systems Inc.
1850 Ramtron Drive, Colorado Springs, CO
Telephone
(800) 545-DRAM;
Fax
(719) 488-9095; http://wwwcsn.net/ramtron/enhanced
80921
38-2105-001
The information contained herein is subject to change wthout notice.
Enhanced reserves the right to change or discontinue this product wthout notice.
Features
I
8Kbit SRAMCache Memory for 12ns RandomReads Wthin Four
Active Pages (Multibank Cache)
I
Fast 4Mbit DRAMArray for 30ns Access to Any NewPage
I
Write Posting Register for 12ns RandomWrites and Burst Writes
Wthin a Page (Hit or Mss)
I
5ns Output Enable Access Time Allows Fast Interleaving
I
256-byte Wde DRAMto SRAMBus for 14.2 Ggabytes/Sec Cache Fill
I
On-chip Cache Hit/Mss Comparators Maintain Cache Coherency
Wthout the Need for External Cache Control
I
A Hit Pin Outputs Status of On-chip Page Hit/Mss Comparators to
Simplify Control
I
Output Latch Enable Allows Extended Data Output (EDO) For
Faster SystemOperation
I
Hidden Precharge Cycles
I
Hidden Refresh Cycles
I
Write-per-bit Option (DM2213) for Parity and Video Applications
I
Extended 64ms Refresh Period for LowStandby Power
I
Standard CMOS/TTL Compatible I/OLevels and +5 Volt Supply
I
LowProfile 300-Ml 44-Pin TSOP-II Package
I
Industrial Temperature Range Option
Description
The Enhanced Memory Systems 4Mb EDRAMcombines raw
speed wth innovative architecture to offer the optimumcost-
performance solution for high performance local or main memory in
computer and embedded control systems. In most high speed
applications, zero-wait-state operation can be achieved wthout
secondary SRAMcache for systemclock speeds of up to 83MHz
wthout interleaving or 132MHz wth two-way interleaving. The
EDRAMoutperforms conventional SRAMcache plus DRAMor
synchronous DRAMmemory systems by mnimzing wait states on
initial reads (hit or mss) and by elimnating writeback delays.
Architectural simlarity wth JEDEC DRAMs allows a single memory
controller design to support either slowJEDEC DRAMs or high speed
EDRAMs. A systemdesigned in this manner can provide a simple
upgrade path to higher systemperformance.
The 512K x 8 EDRAMhas the same control and address interface
as Enhanceds 4Mx 1 and 1Mx 4 EDRAMproducts so that EDRAMs
of different organizations can be supported wth the same controller
design. The 512K x 8 EDRAMimplements the followng additional
features which can be supported on newdesigns:
I
A controllable output latch provides an extended data out (EDO)
mode.
I
Cache size is increased from2Kbits to 8Kbits. The 8Kbit cache is
organized as four 256 x 8 direct mapped rowregisters.
I
A hit pin is provided to tell the memory controller when a hit
occurs to one of the on-chip cache rowregisters.
Archtecture
The EDRAMarchitecturehas a simple integrated SRAMcache
which allows it to operate much like a page mode or static column
DRAM
/CAL
A
0
- A
10
W/R
/F
/RE
V
V
Sense Amps
& Column Write Select
Column Decoder
Row
Address
Latch
CC
SS
A
0
- A
9
4 - 256 X 8 Cache Pages
(Row Registers)
Memory
Array
(2048 X 256 X 8)
A
0
- A
7
/G
/S
/WE
DQ - DQ
7
Column
Address
Latch
4 - 9 Bit
Comparators
I/O
Control
and
Data
Latches
Refresh
Counter
R
Row Adress
and
Refresh
Control
/HIT
4 - Last Row
Read Address
Latches
QLE
Functional Dagram
1
2
3
4
5
6
7
9
10
11
12
13
42
41
40
39
38
37
36
34
33
32
31
30
29
28
27
26
25
24
23
14
15
16
17
18
19
20
21
22
V
8
35
43
44
CC
/F
V
SS
DQ
0
V
CC
DQ
1
DQ
2
V
SS
DQ
3
QLE
V
CC
/G
DQ
4
V
SS
DQ
5
DQ
6
V
CC
DQ
7
V
SS
NC
NC
V
CC
V
SS
W/R
/S
A
10
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
/RE
/CAL
V
CC
A
3
A
2
A
1
A
0
/WE
NC
/HIT
V
SS
Pin Configuration
Enhanced
Memory Systems Inc.
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