- 您現在的位置：買賣IC網 > PDF目錄376778 > DM7476N (FAIRCHILD SEMICONDUCTOR CORP) Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs PDF資料下載
參數資料
| 型號： | DM7476N |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs |
| 中文描述： | TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-16 |
| 文件頁數： | 1/4頁 |
| 文件大?。?/td> | 41K |
| 代理商： | DM7476N |
2000 Fairchild Semiconductor Corporation
DS006528
www.fairchildsemi.com
September 1986
Revised February 2000
D
DM7476
Dual Master-Slave J-K Flip-Flops with
Clear, Preset, and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop after a complete clock
pulse. While the clock is LOW the slave is isolated from the
master. On the positive transition of the clock, the data
from the J and K inputs is transferred to the master. While
the clock is HIGH the J and K inputs are disabled. On the
negative transition of the clock, the data from the master is
transferred to the slave. The logic state of J and K inputs
must not be allowed to change while the clock is HIGH.
The data is transferred to the outputs on the falling edge of
the clock pulse. A LOW logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.
Ordering Code:
Connection Diagram
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
=
Positive pulse data. The J and K inputs must be held constant while
the clock is HIGH. Data is transferred to the outputs on the falling
edge of the clock pulse.
Q
0
=
The output logic level before the indicated input conditions were
established.
Toggle
=
Each output changes to the complement of its previous level on
each complete active HIGH level clock pulse.
Note 1:
This configuration is nonstable; that is, it will not persist when the
preset and/or clear inputs return to their inactive (HIGH) level.
Order Number
DM7476N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
PR
L
H
L
CLR
H
L
L
CLK
X
X
X
J
X
X
X
K
X
X
X
Q
H
L
H
Q
L
H
H
(Note 1)
Q
0
H
L
(Note 1)
Q
0
L
H
H
H
H
H
H
H
H
H
L
H
L
H
L
L
H
H
Toggle
相關PDF資料 |
PDF描述 |
|---|---|
| DM7486 | Quad 2-Input Exclusive-OR Gate(四2輸入異或門) |
| DM7486N | Quad 2-Input Exclusive-OR Gate |
| DM7490A | Decade and Binary Counters(十進制和二進制計數器) |
| DM7490AN | Decade and Binary Counters |
| DM74ALS00 | Quad 2-Input NAND Gate |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DM7476N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| DM7476N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| DM7476W | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs |
| DM7483J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Binary Adder |
| DM7483N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Binary Adder |
發布緊急采購，3分鐘左右您將得到回復。