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參數資料
| 型號： | DM74ALS138SJX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3-To-8-Line Demultiplexer |
| 中文描述： | ALS SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
| 封裝： | 5.30 MM, EIAJ TYPE2, SOP-16 |
| 文件頁數： | 1/6頁 |
| 文件大?。?/td> | 66K |
| 代理商： | DM74ALS138SJX |
2000 Fairchild Semiconductor Corporation
DS006111
www.fairchildsemi.com
September 1986
Revised February 2000
D
DM74ALS138
3 to 8 Line Decoder/Demultiplexer
General Description
These Schottky-clamped circuits are designed to be used
in high-performance memory-decoding or data-routing
applications, requiring very short propagation delay times.
In high-performance memory systems these decoders can
be used to minimize the effects of system decoding. When
used with high-speed memories, the delay times of these
decoders are usually less than the typical access time of
the memory. This means that the effective system delay
introduced by the decoder is negligible.
The DM74ALS138 decodes one-of-eight lines, based upon
the conditions at the three binary select inputs and the
three enable inputs. Two active-LOW and one active-HIGH
enable inputs reduce the need for external gates or invert-
ers when expanding. A 24-line decoder can be imple-
mented with no external inverters, and 32-line decoder
requires only one inverter. An enable input can be used as
a data input for demultiplexing applications.
This decoder/demultiplexer features fully buffered inputs,
presenting only one normalized load to its driving circuit. All
inputs are clamped with high-performance Schottky diodes
to suppress line-ringing and simplify system design.
Features
I
Designed specifically for high speed:
Memory decoders
Data transmission systems
I
3- to 8-line decoder incorporates 3 enable inputs to sim-
plify cascading and/or data reception
I
Low power dissipation…23 mW typ
I
Switching specifications guaranteed over full tempera-
ture and V
CC
range
I
Advanced oxide-isolated, ion-implanted Schottky TTL
process
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Note 1:
G2
=
G2A
+
G2B
Order Number
DM74ALS138M
DM74ALS138SJ
DM74ALS138N
Package Number
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Enable
Select
Outputs
Inputs
Inputs
G1
G2
(Note 1)
H
X
L
L
L
L
L
L
L
L
C
B
A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
L
H
H
H
H
H
H
H
H
X
X
L
L
L
L
H
H
H
H
X
X
L
L
H
H
L
L
H
H
X
X
L
H
L
H
L
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
相關PDF資料 |
PDF描述 |
|---|---|
| DM74ALS14 | Replaced by SN74LVC74A : Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear And Preset 14-SOIC -40 to 85 |
| DM74ALS14M | Hex Inverter with Schmitt Trigger Inputs |
| DM74ALS14SJX | CERAMIC CHIP/MIL-PRF-55681 |
| DM74ALS14N | Hex Inverter with Schmitt Trigger Inputs |
| DM74ALS14SJ | Hex Inverter with Schmitt Trigger Inputs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DM74ALS13J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 4-input NAND Gate |
| DM74ALS13M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 4-input NAND Gate |
| DM74ALS13M/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 4-input NAND Gate |
| DM74ALS13M/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 4-input NAND Gate |
| DM74ALS13N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 4-input NAND Gate |
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