- 您現在的位置：買賣IC網 > PDF目錄376780 > DM74ALS165N (FAIRCHILD SEMICONDUCTOR CORP) Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset 14-TSSOP -40 to 85 PDF資料下載
參數資料
| 型號： | DM74ALS165N |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset 14-TSSOP -40 to 85 |
| 中文描述： | ALS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-16 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 63K |
| 代理商： | DM74ALS165N |
2000 Fairchild Semiconductor Corporation
DS006712
www.fairchildsemi.com
January 1986
Revised February 2000
D
DM74ALS165
8-Bit Parallel In/Serial Out Shift Register
General Description
The DM74ALS165 is an 8-bit serial register that, when
clocked, shifts the data toward serial output, Q
H
. Parallel-in
access to each stage is provided by eight individual direct
data inputs that are enabled by a low level at the SH/LD
input. The DM74ALS165 also features a clock inhibit func-
tion and a complemented serial output, Q
H
.
Clocking is accomplished by a LOW-to-HIGH transition of
the CLK input while SH/LD is held HIGH and CLK INH is
held LOW. The functions of the CLK and CLK INH (clock
inhibit) inputs are interchangeable. Since a LOW CLK input
and a LOW-to-HIGH transition of CLK INH will also accom-
plish clocking, CLK INH should be changed to the high
level only while the CLK input is HIGH. Parallel loading is
inhibited when SH/LD is held HIGH. The parallel inputs to
the register are enabled while SH/LD is LOW indepen-
dently of the levels of CLK, CLK INH, or SER inputs.
Features
I
Complementary outputs
I
Direct overriding load (data) inputs
I
Gated clock inputs
I
Parallel-to-serial data conversion
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Level (steady-state),
L
=
LOW Level (steady-state)
X
=
Don't Care (any input, including transitions)
↑
=
Transition from LOW-to-HIGH level
a...h
=
The level of steady-state input at inputs A through H, respectively
Q
A0
, Q
B0
, Q
H0
=
The level of Q
A
, Q
B
, or Q
H
, respectively, before the
indicated steady-state input conditions were established
Q
An
, Q
Gn
=
The level of Q
A
or Q
G
, respectively, before the most recent
↑
transition of the clock
Order Number
DM74ALS165M
DM74ALS165N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Internal
Outputs
Q
A
a
Q
A0
H
L
H
L
Q
A0
Shift/ Clock Clock Serial Parallel
Load Inhibit
L
X
X
H
L
L
H
L
↑
H
L
↑
H
↑
L
H
↑
L
H
H
X
Output
Q
H
h
Q
H0
Q
Gn
Q
Gn
Q
Gn
Q
Gn
Q
H0
A...H
Q
B
b
Q
B0
Q
An
Q
An
Q
An
Q
An
Q
B0
X
X
H
L
H
L
X
a...h
X
X
X
X
X
X
相關PDF資料 |
PDF描述 |
|---|---|
| DM74ALS169 | Synchronous Four-Bit Up/Down Counters |
| DM74ALS169B | Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset 14-VQFN -40 to 85 |
| DM74ALS169BMX | Synchronous Up/Down Counter |
| DM74ALS174 | Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset 14-VQFN -40 to 85 |
| DM74ALS174M | Hex/Quad D-Type Flip-Flops with Clear |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DM74ALS165N_Q | 功能描述:計數器移位寄存器 8-Bit Shift Register RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| DM74ALS165NX | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:8-Bit Parallel In/Serial Out Shift Register |
| DM74ALS166M | 制造商:Texas Instruments 功能描述: |
| DM74ALS168BJ/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up/Down Counter |
| DM74ALS168BM/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up/Down Counter |
發布緊急采購，3分鐘左右您將得到回復。