
2000 Fairchild Semiconductor Corporation
DS006210
www.fairchildsemi.com
September 1986
Revised February 2000
D
DM74ALS240A DM74ALS241A
Octal 3-STATE Bus Driver
General Description
These octal 3-STATE bus drivers are designed to provide
the designer with flexibility in implementing a bus interface
with memory, microprocessor, or communication systems.
The output 3-STATE gating control is organized into two
separate groups of four buffers. The DM74ALS240A con-
trol inputs symmetrically enable the respective outputs
when set logic LOW, while the DM74ALS241A has comple-
mentary enable gating. The 3-STATE circuitry contains a
feature that maintains the buffer outputs in 3-STATE (high
impedance state) during power supply ramp-up or ramp-
down. This eliminates bus glitching problems that arise
during power-up and power-down.
Features
I
Advanced low power oxide-isolated ion-implanted
Schottky TTL process
I
Functional and pin compatible with the DM74LS coun-
terpart
I
Improved switching performance with less power dissi-
pation compared with the DM74LS counterpart
I
Switching response specified into 500
and 50 pF load
I
Switching response specifications guaranteed over full
temperature and V
CC
supply range
I
PNP input design reduces input loading
I
Low level drive current: 74ALS
=
24 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
DM74ALS240A
DM74ALS241A
Order Number
DM74ALS240AWM
DM74ALS240ASJ
DM74ALS240AN
DM74ALS241AWM
DM74ALS241AN
Package Number
M20B
M20D
N20A
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide