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參數資料
| 型號： | DM74LS166M |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad Buffer with 3-STATE Outputs; Package: TSSOP; No of Pins: 14; Container: Rail |
| 中文描述： | LS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 78K |
| 代理商： | DM74LS166M |
2000 Fairchild Semiconductor Corporation
DS006400
www.fairchildsemi.com
August 1986
Revised March 2000
D
DM74LS166
8-Bit Parallel-In/Serial-Out Shift Register
General Description
These parallel-in or serial-in, serial-out shift registers fea-
ture gated clock inputs and an overriding clear input. All
inputs are buffered to lower the drive requirements to one
normalized load, and input clamping diodes minimize
switching transients to simplify system design. The load
mode is established by the shift/load input. When HIGH,
this input enables the serial data input and couples the
eight flip-flops for serial shifting with each clock pulse.
When LOW, the parallel (broadside) data inputs are
enabled and synchronous loading occurs on the next clock
pulse. During parallel loading, serial data flow is inhibited.
Clocking is accomplished on the LOW-to-HIGH level edge
of the clock pulse through a two-input NOR gate, permitting
one input to be used as a clock-enable or clock-inhibit func-
tion. Holding either of the clock inputs HIGH inhibits clock-
ing; holding either LOW enables the other clock input. This
allows the system clock to be free running, and the register
can be stopped on command with the other clock input.
The clock-inhibit input should be changed to the high level
only while the clock input is HIGH. A buffered, direct clear
input overrides all other inputs, including the clock, and
sets all flip-flops to zero.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
DM74LS166M
DM74LS166WM
DM74LS166N
Package Number
M16A
M16B
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
相關PDF資料 |
PDF描述 |
|---|---|
| DM74LS166N | Quad Buffer with 3-STATE Outputs; Package: TSSOP; No of Pins: 14; Container: Tape & Reel |
| DM74LS166WM | Quad Buffer with 3-STATE Outputs |
| DM74LS166 | 8-Bit Parallel-In/Serial-Out Shift Register(8位并行輸入/串行輸出的移位寄存器) |
| DM74LS169 | Quad Buffer with 3-STATE Outputs; Package: SOIC; No of Pins: 14; Container: Rail |
| DM74LS169A | Quad Buffer with 3-STATE Outputs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DM74LS166MX | 功能描述:計數器移位寄存器 8-Bit Serial Sht Reg RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| DM74LS166N | 功能描述:計數器移位寄存器 8-Bit Serial Sht Reg RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| DM74LS166WM | 功能描述:計數器移位寄存器 DISC BY MFG 7/03 RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| DM74LS166WMX | 功能描述:計數器移位寄存器 8-Bit Serial Sht Reg RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| DM74LS169A WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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