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參數(shù)資料
| 型號： | DM74LS73A |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs(帶清零和互補輸出的雙負邊緣觸發(fā)的主-從J-K觸發(fā)器) |
| 中文描述： | 雙下降沿觸發(fā)主從JK觸發(fā)器明確和互補輸出（帶清零和互補輸出的雙負邊緣觸發(fā)的主-從JK觸發(fā)器） |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 53K |
| 代理商： | DM74LS73A |
2000 Fairchild Semiconductor Corporation
DS006372
www.fairchildsemi.com
August 1986
Revised March 2000
D
DM74LS73A
Dual Negative-Edge-Triggered Master-Slave
J-K Flip-Flops with Clear and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. The data on the J
and K inputs is allowed to change while the clock is HIGH
or LOW without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the clear
input will reset the outputs regardless of the levels of the
other inputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
↓
=
Negative going edge of pulse.
Q
0
=
The output logic level before the indicated input conditions were
established.
Toggle
=
Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
Order Number
DM74LS73AM
DM74LS73AN
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
CLR
L
H
H
H
H
CLK
X
↓
↓
↓
↓
H
J
X
L
H
L
H
K
X
L
L
H
H
Q
L
Q
0
H
L
Q
H
Q
0
L
H
Toggle
H
X
X
Q
0
Q
0
相關PDF資料 |
PDF描述 |
|---|---|
| DM74LS73AM | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs |
| DM74LS73AN | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs |
| DM74LS73AMX | J-K-Type Flip-Flop |
| DM74LS74A | Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs(帶清零和互補輸出的雙負邊緣觸發(fā)的主-從J-K觸發(fā)器) |
| DM74LS74 | Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DM74LS73A WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| DM74LS73AM | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74LS73AN | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74LS74 WAF | 制造商:Texas Instruments 功能描述: |
| DM74LS74A WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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