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參數(shù)資料
| 型號： | DM74S182N |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Look-Ahead Carry Generator |
| 中文描述： | S SERIES, 4-BIT LOOK-AHEAD CARRY GENERATOR, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-16 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 53K |
| 代理商： | DM74S182N |
2000 Fairchild Semiconductor Corporation
DS006474
www.fairchildsemi.com
August 1986
Revised March 2000
D
DM74S182
Look-Ahead Carry Generator
General Description
These circuits are high-speed, look-ahead carry genera-
tors, capable of anticipating a carry across four binary
adders or groups of adders. They are cascadable to per-
form full look-ahead across n-bit adders. Carry, generate-
carry, and propagate-carry functions are provided as
shown in the pin designation table.
When used in conjunction with the 181 arithmetic logic unit,
these generators provide high-speed carry look-ahead
capability for any word length. Each DM74S182 generates
the look-ahead (anticipated carry) across a group of four
ALU’s and, in addition, other carry look-ahead circuits may
be employed to anticipate carry across sections of four
look-ahead packages up to n-bits. The method of cascad-
ing circuits to perform multi-level look-ahead is illustrated
under typical application data.
Carry input and output of the ALU’s are in their true form,
and the carry propagate (P) and carry generate (G) are in
negated form; therefore, the carry functions (inputs, out-
puts, generate, and propagate) of the look-ahead genera-
tors are implemented in the compatible forms for direct
connection to the ALU. Reinterpretations of carry functions,
as explained on the 181 data sheet are also applicable to
and compatible with the look-ahead generator. Positive
logic equations for the DM74S182 are:
C
n
+
x
=
G0
+
P0 C
n
C
n
+
y
=
G1
+
P1 G0
+
P1 P0 C
n
C
n
+
z
=
G2
+
P2 G1
+
P2 P1 G0
+
P2 P1 P0 C
n
G
=
G3 (P3
+
G2) (P3
+
P2
+
G1)
(P3
+
P2
+
P1
+
G0)
P
=
P3 P2 P1 P0
Features
I
Typical propagation delay time 7 ns
I
Typical power dissipation 260 mW
Ordering Code:
Connection Diagram
Pin Designations
Order Number
DM74S182N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Designation
G0, G1, G2, G3
Pin Nos.
3, 1, 14, 5
Function
Active LOW
Carry Generate Inputs
Active LOW
Carry Propagate Inputs
Carry Input
Carry Outputs
P0, P1, P2, P3
4, 2, 15, 6
C
n
13
C
n
+
x
, C
n
+
y
,
C
n
+
z
G
12, 11, 9
10
Active LOW
Carry Generate Output
Active LOW
Carry Propagate Output
Supply Voltage
Ground
P
7
V
CC
GND
16
8
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