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參數資料
| 型號： | DM74S280 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 9-Bit Parity Generator/Checker |
| 中文描述： | 9位奇偶發生器/檢查 |
| 文件頁數： | 1/5頁 |
| 文件大小： | 62K |
| 代理商： | DM74S280 |
2000 Fairchild Semiconductor Corporation
DS006483
www.fairchildsemi.com
August 1986
Revised May 2000
D
DM74S280
9-Bit Parity Generator/Checker
General Description
These universal, nine-bit parity generators/checkers utilize
Schottky-clamped TTL high-performance circuitry, and fea-
ture odd/even outputs to facilitate operation of either odd or
even parity applications. The word-length capability is eas-
ily expanded by cascading.
The DM74S280 can be used to upgrade the performance
of most systems utilizing the DM74180 parity generator/
checker. Although the DM74S280 is implemented without
expander inputs, the corresponding function is provided by
the availability of all input at pin 4, and no internal connec-
tion at pin 3. This permits the DM74S280 to be substituted
for the 180 in existing designs to produce an identical func-
tion, even if DM74S280’s are mixed with existing 180’s.
Input buffers are provided so that each input represents
only one normal 74S load, and full fan-out to 10 normal
Series 74S loads is available from each of the outputs at
low logic levels. A fan-out to 20 normal Series 74S loads is
provided at high logic levels, to facilitate connection of
unused inputs to used inputs.
Features
I
Generates either odd or even parity for nine data lines
I
Cascadable for N-bits
I
Can be used to upgrade existing systems using MSI par-
ity circuits
I
Typical data-to-output delay
—
14 ns
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter
“
X
”
to the ordering code.
Connection Diagram
Function Table
Order Number
DM74S280M
DM74S280N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Number of Inputs
(A Thru I) that are HIGH
0, 2, 4, 6, 8
1, 3, 5, 7, 9
Outputs
∑
Even
H
L
∑
Odd
L
H
相關PDF資料 |
PDF描述 |
|---|---|
| DM74S280M | 9-Bit Parity Generator/Checker |
| DM74S280N | 9-Bit Parity Generator/Checker |
| DM74S280MX | Parity Generator/Checker |
| DM74S283 | 4-Bit Binary Adder with Fast Carry |
| DM74S283N | 4-Bit Binary Adder with Fast Carry |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DM74S280 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| DM74S280J | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DM74S280M | 功能描述:奇偶功能 9-Bit Par Gen/Check RoHS:否 制造商:Texas Instruments 電路數量:1 位數:9 邏輯系列:74AC 封裝 / 箱體:SOIC-14 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:263 ns 工作電源電壓:1.8 V, 2.5 V, 3.3 V, 5 V 最大工作溫度:+ 70 C 最小工作溫度:- 55 C 封裝:Reel |
| DM74S280N | 功能描述:奇偶功能 9-Bit Par Gen/Check RoHS:否 制造商:Texas Instruments 電路數量:1 位數:9 邏輯系列:74AC 封裝 / 箱體:SOIC-14 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:263 ns 工作電源電壓:1.8 V, 2.5 V, 3.3 V, 5 V 最大工作溫度:+ 70 C 最小工作溫度:- 55 C 封裝:Reel |
| DM74S283 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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