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參數資料
| 型號： | DM81LS97AN |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3-STATE Octal Buffer |
| 中文描述： | LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20 |
| 封裝： | 0.300 INCH, MS-001, PLASTIC, DIP-20 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 71K |
| 代理商： | DM81LS97AN |
1999 Fairchild Semiconductor Corporation
DS006435
www.fairchildsemi.com
September 1991
Revised May 1999
D
DM81LS95A DM81LS96A DM81LS97A
3-STATE Octal Buffer
General Description
These devices provide eight, two-input buffers in each
package. All employ low-power-Schottky TTL technology.
One of the two inputs to each buffer is used as a control
line to gate the output into the high-impedance state, while
the other input passes the data through the buffer. The
DM81LS95A and DM81LS97A present true data at the out-
puts, while the DM81LS96A is inverting. On the
DM81LS95A and DM81LS96A versions, all eight 3-STATE
enable lines are common, with access through a 2-input
NOR gate. On the DM81LS97A version, four buffers are
enabled from one common line, and the other four buffers
are enabled form another common line. In all cases the
outputs are placed in the 3-STATE condition by applying a
high logic level to the enable pins.
Features
I
Typical power dissipation
DM81LS95A, DM81LS97A
DM81LS96A
I
Typical propagation delay
DM81LS95A, DM81LS97A
DM81LS96A
I
Low power-Schottky, 3-STATE technology
80 mW
65 mW
15 ns
10 ns
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
DM81LS95A and DM92LS96A
Note 1:
Both G1 and G2 must be LOW for outputs to be enabled.
DM81LS97A
Order Number
DM81LS95AWM
DM81LS95AN
DM81LS96AWM
DM81LS96AN
DM81LS97AN
Package Number
M20B
N20A
M20B
N20A
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
A1–A8
Y1–Y8
Descriptions
Inputs
Outputs
G1–G2
Active LOW Output Enables (Note 1)
Pin Names
A1–A8
Y1–Y8
Descriptions
Inputs
Outputs
G1
Active LOW Output Enable (Y1–Y4)
G2
Active LOW Output Enable (Y5–Y8)
相關PDF資料 |
PDF描述 |
|---|---|
| DM81LS96A | 3-STATE Octal Buffer(三態輸出的八緩沖器) |
| DM81LS97A | 3-STATE Octal Buffer(三態輸出的八緩沖器) |
| DM81LS95AWMX | 8-Bit Non-Inverting Buffer/Driver |
| DM81LS96AWMX | 8-Bit Inverting Buffer/Driver |
| DM81LS97W | Dual 4-Bit Non-Inverting Buffer/Driver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DM81LS97AN/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 4-Bit Non-Inverting Buffer/Driver |
| DM81LS97AN/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 4-Bit Non-Inverting Buffer/Driver |
| DM81LS97AWM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:TRI-STATE Octal Buffer |
| DM81LS97J | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Three-State Octal Buffers |
| DM81LS97J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 4-Bit Non-Inverting Buffer/Driver |
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